2-16 Vol. 3A

SYSTEM ARCHITECTURE OVERVIEW

EM

Emulation (bit 2 of CR0) — Indicates that the processor does not have an internal or external x87 FPU 
when set; indicates an x87 FPU is present when clear. This flag also affects the execution of 
MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
When the EM flag is set, execution of an x87 FPU instruction generates a device-not-available exception 
(#NM). This flag must be set when the processor does not have an internal x87 FPU or is not connected to 
an external math coprocessor. Setting this flag forces all floating-point instructions to be handled by soft-
ware emulation. Table 9-3 shows the recommended setting of this flag, depending on the IA-32 processor 
and x87 FPU or math coprocessor present in the system. Table 2-2 shows the interaction of the EM, MP, and 
TS flags.
Also, when the EM flag is set, execution of an MMX instruction causes an invalid-opcode exception (#UD) 
to be generated (see Table 12-1). Thus, if an IA-32 or Intel 64 processor incorporates MMX technology, the 
EM flag must be set to 0 to enable execution of MMX instructions.
Similarly for SSE/SSE2/SSE3/SSSE3/SSE4 extensions, when the EM flag is set, execution of most 
SSE/SSE2/SSE3/SSSE3/SSE4 instructions causes an invalid opcode exception (#UD) to be generated (see 
Table 13-1). If an IA-32 or Intel 64 processor incorporates the SSE/SSE2/SSE3/SSSE3/SSE4 extensions, 
the EM flag must be set to 0 to enable execution of these extensions. SSE/SSE2/SSE3/SSSE3/SSE4 
instructions not affected by the EM flag include: PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, 
CLFLUSH, CRC32, and POPCNT.

MP

Monitor Coprocessor (bit 1 of CR0) — Controls the interaction of the WAIT (or FWAIT) instruction with the 
TS flag (bit 3 of CR0). If the MP flag is set, a WAIT instruction generates a device-not-available exception 
(#NM) if the TS flag is also set. If the MP flag is clear, the WAIT instruction ignores the setting of the TS flag. 
Table 9-3 shows the recommended setting of this flag, depending on the IA-32 processor and x87 FPU or 
math coprocessor present in the system. Table 2-2 shows the interaction of the MP, EM, and TS flags.

PE

Protection Enable (bit 0 of CR0) — Enables protected mode when set; enables real-address mode when 
clear. This flag does not enable paging directly. It only enables segment-level protection. To enable paging, 
both the PE and PG flags must be set. 
See also: Section 9.9, “Mode Switching.”

PCD 

Page-level Cache Disable (bit 4 of CR3) — Controls the memory type used to access the first paging 
structure of the current paging-structure hierarchy. See Section 4.9, “Paging and Memory Typing”. This bit 
is not used if paging is disabled, with PAE paging, or with IA-32e paging if CR4.PCIDE=1.

PWT

Page-level Write-Through (bit 3 of CR3) — Controls the memory type used to access the first paging 
structure of the current paging-structure hierarchy. See Section 4.9, “Paging and Memory Typing”. This bit 
is not used if paging is disabled, with PAE paging, or with IA-32e paging if CR4.PCIDE=1.

VME

Virtual-8086 Mode Extensions (bit 0 of CR4) — Enables interrupt- and exception-handling extensions 
in virtual-8086 mode when set; disables the extensions when clear. Use of the virtual mode extensions can 
improve the performance of virtual-8086 applications by eliminating the overhead of calling the virtual-
8086 monitor to handle interrupts and exceptions that occur while executing an 8086 program and, 
instead, redirecting the interrupts and exceptions back to the 8086 program’s handlers. It also provides 

Table 2-2.  Action Taken By x87 FPU Instructions for Different Combinations of EM, MP, and TS

CR0 Flags

x87 FPU Instruction Type

EM

MP

TS

Floating-Point WAIT/FWAIT

0

0

0

Execute

Execute.

0

0

1

#NM  Exception

Execute.

0

1

0

Execute

Execute.

0

1

1

#NM Exception

#NM exception.

1

0

0

#NM  Exception

Execute.

1

0

1

#NM  Exception

Execute.

1

1

0

#NM  Exception

Execute.

1

1

1

#NM Exception

#NM exception.