Vol. 3A 2-17

SYSTEM ARCHITECTURE OVERVIEW

hardware support for a virtual interrupt flag (VIF) to improve reliability of running 8086 programs in multi-
tasking and multiple-processor environments.
See also: Section 20.3, “Interrupt and Exception Handling in Virtual-8086 Mode.”

PVI

Protected-Mode Virtual Interrupts (bit 1 of CR4) — Enables hardware support for a virtual interrupt 
flag (VIF) in protected mode when set; disables the VIF flag in protected mode when clear. 
See also: Section 20.4, “Protected-Mode Virtual Interrupts.”

TSD

Time Stamp Disable (bit 2 of CR4) — Restricts the execution of the RDTSC instruction to procedures 
running at privilege level 0 when set; allows RDTSC instruction to be executed at any privilege level when 
clear. This bit also applies to the RDTSCP instruction if supported (if CPUID.80000001H:EDX[27] = 1).

DE

Debugging Extensions (bit 3 of CR4) — References to debug registers DR4 and DR5 cause an unde-
fined opcode (#UD) exception to be generated when set; when clear, processor aliases references to regis-
ters DR4 and DR5 for compatibility with software written to run on earlier IA-32 processors. 
See also: Section 17.2.2, “Debug Registers DR4 and DR5.”

PSE

Page Size Extensions (bit 4 of CR4) — Enables 4-MByte pages with 32-bit paging when set; restricts 
32-bit paging to pages of 4 KBytes when clear.
See also: Section 4.3, “32-Bit Paging.”

PAE

Physical Address Extension (bit 5 of CR4) — When set, enables paging to produce physical addresses 
with more than 32 bits. When clear, restricts physical addresses to 32 bits. PAE must be set before entering 
IA-32e mode.
See also: Chapter 4, “Paging.”

MCE

Machine-Check Enable (bit 6 of CR4) — Enables the machine-check exception when set; disables the 
machine-check exception when clear.
See also: Chapter 15, “Machine-Check Architecture.”

PGE

Page Global Enable (bit 7 of CR4) — (Introduced in the P6 family processors.) Enables the global page 
feature when set; disables the global page feature when clear. The global page feature allows frequently 
used or shared pages to be marked as global to all users (done with the global flag, bit 8, in a page-direc-
tory or page-table entry). Global pages are not flushed from the translation-lookaside buffer (TLB) on a 
task switch or a write to register CR3.
When enabling the global page feature, paging must be enabled (by setting the PG flag in control register 
CR0) before the PGE flag is set. Reversing this sequence may affect program correctness, and processor 
performance will be impacted. 
See also: Section 4.10, “Caching Translation Information.”

PCE

Performance-Monitoring Counter Enable (bit 8 of CR4) — Enables execution of the RDPMC instruc-
tion for programs or procedures running at any protection level when set; RDPMC instruction can be 
executed only at protection level 0 when clear.

OSFXSR

Operating System Support for FXSAVE and FXRSTOR instructions (bit 9 of CR4) — When set, this 
flag: (1) indicates to software that the operating system supports the use of the FXSAVE and FXRSTOR 
instructions, (2) enables the FXSAVE and FXRSTOR instructions to save and restore the contents of the 
XMM and MXCSR registers along with the contents of the x87 FPU and MMX registers, and (3) enables the 
processor to execute SSE/SSE2/SSE3/SSSE3/SSE4 instructions, with the exception of the PAUSE, 
PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32, and POPCNT. 
If this flag is clear, the FXSAVE and FXRSTOR instructions will save and restore the contents of the x87 FPU 
and MMX registers, but they may not save and restore the contents of the XMM and MXCSR registers. Also, 
the processor will generate an invalid opcode exception (#UD) if it attempts to execute any 
SSE/SSE2/SSE3 instruction, with the exception of PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, 
MOVNTI, CLFLUSH, CRC32, and POPCNT. The operating system or executive must explicitly set this flag.