Page 1977

Instructions

operands

reserved bits

1-6

segmented addressing

NT (nested task) flag

EFLAGS register

2-10

7-10

7-12

Null segment selector, checking for

5-6

Numeric overflow exception (#O)

22-9

Numeric underflow exception (#U)

22-10

NV (invert) flag, PerfEvtSel0 MSR

(P6 family processors)

18-4

18-117

NW (not write-through) flag

CR0 control register

NXE bit

Obsolete instructions

22-5

22-14

OF flag, EFLAGS register

6-24

On die digital thermal sensor

relevant MSRs

sensor enumeration

On-Demand

clock modulation enable bits

14-23

On-demand

clock modulation duty cycle bits

14-23

On-die sensors

14-19

Opcodes

undefined

22-5

Operands

instruction

operand-size prefix

21-1

Operating modes

64-bit mode

compatibility mode

IA-32e mode

introduction to

protected mode

SMM (system management mode)

2-7

transitions between

2-8

virtual-8086 mode

2-7

VMX operation

enabling and entering

23-3

guest environments

31-1

OR instruction

8-3

OS (operating system mode) flag

PerfEvtSel0 and PerfEvtSel1 MSRs (P6 only)

18-4

18-116

OSFXSR (FXSAVE/FXRSTOR support) flag

CR4 control register

2-17

9-8

13-2

OSXMMEXCPT (SIMD floating-point exception support) flag, CR4 control

OUT instruction

Out-of-spec status bit

14-29

Out-of-spec status log

14-26

14-29

OUTS/OUTSB/OUTSW/OUTSD instruction

17-9

25-2

Overflow exception (#OF)

6-24

Overheat interrupt enable bit

14-27

14-30

P (present) flag

page-directory entry

page-table entry

segment descriptor

P5_MC_ADDR MSR

P5_MC_TYPE MSR

P6 family processors

compatibility with FP software

22-6

description of

1-1

last branch, interrupt, and exception recording

17-38

list of performance-monitoring events

19-204

MSR supported by

35-319

PAE paging

feature flag, CR4 register

2-17

flag, CR4 control register

3-6

22-17

22-18

Page attribute table (PAT)

compatibility with earlier IA-32 processors

11-36

detecting support for

11-34

IA32_PAT MSR

11-34

introduction to

11-33

memory types that can be encoded with

11-34

MSR

11-13

precedence of cache controls

11-14

programming

11-35

selecting a memory type with

11-35

Page directories

Page directory

base address (PDBR)

7-5

introduction to

overview

3-2

setting up during initialization

9-10

Page directory pointers

Page frame (see Page)

Page tables

introduction to

overview

3-2

setting up during initialization

9-10

Page-directory entries

8-3

11-5

Page-fault exception (#PF)

4-47

6-40

22-20

Pages

disabling protection of

5-1

enabling protection of

5-1

introduction to