Vol. 3C 35-107

MODEL-SPECIFIC REGISTERS (MSRS)

Table 35-13.  MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec

0H

0

IA32_P5_MC_ADDR

Thread

See Section 35.22, “MSRs in Pentium Processors.”

1H

1

IA32_P5_MC_TYPE

Thread

See Section 35.22, “MSRs in Pentium Processors.”

6H

6

IA32_MONITOR_FILTER_

SIZE

Thread

See Section 8.10.5, “Monitor/Mwait Address Range Determination,” 

and Table 35-2.

10H

16

IA32_TIME_

STAMP_COUNTER

Thread

See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.

17H

23

IA32_PLATFORM_ID

Package

Platform ID (R) 

See Table 35-2.

17H

23

MSR_PLATFORM_ID

Package

Model Specific Platform ID (R) 

49:0

Reserved.

52:50

See Table 35-2.

63:53

Reserved.

1BH

27

IA32_APIC_BASE

Thread

See Section 10.4.4, “Local APIC Status and Location,” and 

Table 35-2.

34H

52

MSR_SMI_COUNT

Thread

SMI Counter (R/O)

31:0

SMI Count (R/O) 
Running count of SMI events since last RESET.

63:32

Reserved.

3AH

58

IA32_FEATURE_CONTROL

Thread

Control Features in Intel 64Processor (R/W)
See Table 35-2.

79H

121

IA32_BIOS_

UPDT_TRIG

Core

BIOS Update Trigger Register (W) 
See Table 35-2.

8BH

139

IA32_BIOS_

SIGN_ID

Thread

BIOS Update Signature ID (RO)
See Table 35-2.

C1H

193

IA32_PMC0

Thread

Performance Counter Register
See Table 35-2.

C2H

194

IA32_PMC1

Thread

Performance Counter Register
See Table 35-2.

C3H

195

IA32_PMC2

Thread

Performance Counter Register
See Table 35-2.

C4H

196

IA32_PMC3

Thread

Performance Counter Register
See Table 35-2.

CEH

206

MSR_PLATFORM_INFO

Package

see http://biosbits.org.

7:0

Reserved.