Vol. 3C 35-143

MODEL-SPECIFIC REGISTERS (MSRS)

Table 35-18.  MSRs Supported by Intel® Processors 

based on Intel® microarchitecture code name Sandy Bridge

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec

0H

0

IA32_P5_MC_ADDR

Thread

See Section 35.22, “MSRs in Pentium Processors.”

1H

1

IA32_P5_MC_TYPE

Thread

See Section 35.22, “MSRs in Pentium Processors.”

6H

6

IA32_MONITOR_FILTER_

SIZE

Thread

See Section 8.10.5, “Monitor/Mwait Address Range Determination,” 

and Table 35-2.

10H

16

IA32_TIME_STAMP_

COUNTER

Thread

See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.

17H

23

IA32_PLATFORM_ID

Package

Platform ID (R) 

See Table 35-2.

1BH

27

IA32_APIC_BASE

Thread

See Section 10.4.4, “Local APIC Status and Location,” and 

Table 35-2.

34H

52

MSR_SMI_COUNT

Thread

SMI Counter (R/O)

31:0

SMI Count (R/O) 
Count SMIs.

63:32

Reserved.

3AH

58

IA32_FEATURE_CONTROL

Thread

Control Features in Intel 64 Processor (R/W)
See Table 35-2.

0

Lock (R/WL) 

1

Enable VMX inside SMX operation (R/WL) 

2

Enable VMX outside SMX operation (R/WL) 

14:8

SENTER local functions enables (R/WL) 

15

SENTER global functions enable (R/WL) 

79H

121

IA32_BIOS_UPDT_TRIG

Core

BIOS Update Trigger Register (W) 
See Table 35-2.

8BH

139

IA32_BIOS_SIGN_ID

Thread

BIOS Update Signature ID (RO)
See Table 35-2.

C1H

193

IA32_PMC0

Thread

Performance Counter Register 
See Table 35-2.

C2H

194

IA32_PMC1

Thread

Performance Counter Register 
See Table 35-2.

C3H

195

IA32_PMC2

Thread

Performance Counter Register 
See Table 35-2.

C4H

196

IA32_PMC3

Thread

Performance Counter Register 
See Table 35-2.

C5H

197

IA32_PMC4

Core

Performance Counter Register (if core not shared by threads)

C6H

198

IA32_PMC5

Core

Performance Counter Register (if core not shared by threads)

C7H

199

IA32_PMC6

Core

Performance Counter Register (if core not shared by threads)

C8H

200

IA32_PMC7

Core

Performance Counter Register (if core not shared by threads)