2-18 Vol. 3A

SYSTEM ARCHITECTURE OVERVIEW

NOTE

CPUID feature flag FXSR indicates availability of the FXSAVE/FXRSTOR instructions. The OSFXSR 
bit provides operating system software with a means of enabling FXSAVE/FXRSTOR to save/restore 
the contents of the X87 FPU, XMM and MXCSR registers. Consequently OSFXSR bit indicates that 
the operating system provides context switch support for SSE/SSE2/SSE3/SSSE3/SSE4.

OSXMMEXCPT

Operating System Support for Unmasked SIMD Floating-Point Exceptions (bit 10 of CR4) — 
When set, indicates that the operating system supports the handling of unmasked SIMD floating-point 
exceptions through an exception handler that is invoked when a SIMD floating-point exception (#XM) is 
generated. SIMD floating-point exceptions are only generated by SSE/SSE2/SSE3/SSE4.1 SIMD floating-
point instructions. 
The operating system or executive must explicitly set this flag. If this flag is not set, the processor will 
generate an invalid opcode exception (#UD) whenever it detects an unmasked SIMD floating-point excep-
tion.

UMIP

User-Mode Instruction Prevention (bit 11 of CR4) — When set, the following instructions cannot be 
executed if CPL > 0: SGDT, SIDT, SLDT, SMSW, and STR. An attempt at such execution causes a general-
protection exception (#GP).

VMXE

VMX-Enable Bit (bit 13 of CR4) — Enables VMX operation when set. See Chapter 23, “Introduction to 
Virtual Machine Extensions.”

SMXE

SMX-Enable Bit (bit 14 of CR4) — Enables SMX operation when set. See Chapter 6, “Safer Mode Exten-
sions Reference” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D.

FSGSBASE

FSGSBASE-Enable Bit (bit 16 of CR4) — Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, 
and WRGSBASE.

PCIDE

PCID-Enable Bit (bit 17 of CR4) — Enables process-context identifiers (PCIDs) when set. See Section 
4.10.1, “Process-Context Identifiers (PCIDs)”. Can be set only in IA-32e mode (if IA32_EFER.LMA = 1).

OSXSAVE

XSAVE and Processor Extended States-Enable Bit (bit 18 of CR4) — When set, this flag: (1) indi-
cates (via CPUID.01H:ECX.OSXSAVE[bit 27]) that the operating system supports the use of the XGETBV, 
XSAVE and XRSTOR instructions by general software; (2) enables the XSAVE and XRSTOR instructions to 
save and restore the x87 FPU state (including MMX registers), the SSE state (XMM registers and MXCSR), 
along with other processor extended states enabled in XCR0; (3) enables the processor to execute XGETBV 
and XSETBV instructions in order to read and write XCR0. See Section 2.6 and Chapter 13, “System 
Programming for Instruction Set Extensions and Processor Extended States”.

SMEP

SMEP-Enable Bit (bit 20 of CR4) — Enables supervisor-mode execution prevention (SMEP) when set. 
See Section 4.6, “Access Rights”.

SMAP

SMAP-Enable Bit (bit 21 of CR4) — Enables supervisor-mode access prevention (SMAP) when set. See 
Section 4.6, “Access Rights.”

PKE

Protection-Key-Enable Bit (bit 22 of CR4) — Enables IA-32e paging to associate each linear address 
with a protection key. The PKRU register specifies, for each protection key, whether user-mode linear 
addresses with that protection key can be read or written. This bit also enables access to the PKRU register 
using the RDPKRU and WRPKRU instructions.

TPL

Task Priority Level (bit 3:0 of CR8) — This sets the threshold value corresponding to the highest-