INDEX
INDEX-4 Vol. 3D
page table base address
,
CR4 control register
description of
,
enabling control functions
,
inclusion in IA-32 architecture
,
introduction to
,
VMX usage of
,
CR8 register
,
64-bit mode
compatibility mode
,
description of
,
task priority level bits
when available
,
CS register
,
state following initialization
C-state
,
CTR0 and CTR1 (performance counters) MSRs (Pentium processor)
,
,
Current privilege level (see CPL)
D
D (default operation size) flag
segment descriptor
,
Data breakpoint exception conditions
Data segments
description of
,
descriptor layout
expand-down type
,
paging of
privilege level checking when accessing
DE (debugging extensions) flag, CR4 control register
,
Debug exception (#DB)
,
,
,
,
DEBUGCTLMSR MSR
,
,
Debugging facilities
breakpoint exception (#BP)
debug exception (#DB)
,
DR6 debug status register
,
DR7 debug control register
exceptions
,
INT3 instruction
last branch, interrupt, and exception recording
,
masking debug exceptions
overview of
performance-monitoring counters
,
registers
description of
,
introduction to
,
loading
RF (resume) flag, EFLAGS
see DS (debug store) mechanism
T (debug trap) flag, TSS
TF (trap) flag, EFLAGS
virtualization
,
VMX operation
,
DEC instruction
,
Denormal operand exception (#D)
Denormalized operand
,
Device-not-available exception (#NM)
,
,
,
,
DFR
Destination Format Register
,
,
Digital readout bits
,
,
DIV instruction
Divide configuration register, local APIC
Divide-error exception (#DE)
,
Double-fault exception (#DF)
,
DPL (descriptor privilege level) field, segment descriptor
,
,
DR0-DR3 breakpoint-address registers
,
DR4-DR5 debug registers
,
DR6 debug status register
B0-B3 (BP detected) flags
BD (debug register access detected) flag
BS (single step) flag
,
BT (task switch) flag
debug exception (#DB)
reserved bits
,
DR7 debug control register
G0-G3 (global breakpoint enable) flags
,
GD (general detect enable) flag
,
GE (global exact breakpoint enable) flag
L0-L3 (local breakpoint enable) flags
LE local exact breakpoint enable) flag
LEN0-LEN3 (Length) fields
R/W0-R/W3 (read/write) fields
DS feature flag, CPUID instruction
,
,
,
DS save area
,
,
,
DS (debug store) mechanism
availability of
description of
DS feature flag, CPUID instruction
DS save area
,
,
IA-32e mode
interrupt service routine (DS ISR)
setting up
,
Dual-core technology
architecture
,
logical processors supported
,
MTRR memory map
,
multi-threading feature flag
,
performance monitoring
specific features
Dual-monitor treatment
D/B (default operation size/default stack pointer size and/or upper bound)
flag, segment descriptor
,
E
E (edge detect) flag
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family)
,
E (edge detect) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family
processors)
E (expansion direction) flag
segment descriptor
E (MTRRs enabled) flag
IA32_MTRR_DEF_TYPE MSR
EFLAGS register
identifying 32-bit processors
introduction to
new flags
,
saved in TSS
system flags
VMX operation
EIP register
saved in TSS
state following initialization
,
EM (emulation) flag
CR0 control register
,
,
,
,
EMMS instruction
Enhanced Intel SpeedStep Technology
ACPI 3.0 specification
,
IA32_APERF MSR
IA32_MPERF MSR
,
IA32_PERF_CTL MSR
IA32_PERF_STATUS MSR
,
introduction
multiple processor cores
performance transitions
,
P-state coordination
,
EOI
End Of Interrupt register