14-2 Vol. 3B

POWER AND THERMAL MANAGEMENT

IA32_APERF MSR. See Figure 14-1 for an overview of the two 64-bit MSRs and the bullets below for a detailed 
description:

•

Use CPUID to check the P-State hardware coordination feedback capability bit. CPUID.06H.ECX[Bit 0] = 1 
indicates IA32_MPERF MSR and IA32_APERF MSR are present.

•

IA32_MPERF MSR (E7H) increments in proportion to a fixed frequency, which is configured when the processor 
is booted.

•

IA32_APERF MSR (E8H) increments in proportion to actual performance, while accounting for hardware coordi-
nation of P-state and TM1/TM2; or software initiated throttling.

•

The MSRs are per logical processor; they measure performance only when the targeted processor is in the C0 
state.

•

Only the IA32_APERF/IA32_MPERF ratio is architecturally defined; software should not attach meaning to the 
content of the individual of IA32_APERF or IA32_MPERF MSRs.

•

When either MSR overflows, both MSRs are reset to zero and continue to increment.

•

Both MSRs are full 64-bits counters. Each MSR can be written to independently. However, software should 
follow the guidelines illustrated in Example 14-1.

If P-states are exposed by the BIOS as hardware coordinated, software is expected to confirm processor support 
for P-state hardware coordination feedback and use the feedback mechanism to make P-state decisions. The OSPM 
is expected to either save away the current MSR values (for determination of the delta of the counter ratio at a later 
time) or reset both MSRs (execute WRMSR with 0 to these MSRs individually) at the start of the time window used 
for making the P-state decision. When not resetting the values, overflow of the MSRs can be detected by checking 
whether the new values read are less than the previously saved values. 
Example 14-1 demonstrates steps for using the hardware feedback mechanism provided by IA32_APERF MSR and 
IA32_MPERF MSR to determine a target P-state.

Example 14-1.  Determine Target P-state From Hardware Coordinated Feedback

DWORD PercentBusy; // Percentage of processor time not idle.

// Measure “PercentBusy“ during previous sampling window.
// Typically, “PercentBusy“ is measure over a time scale suitable for
// power management decisions
// 
// RDMSR of MCNT and ACNT should be performed without delay.
// Software needs to exercise care to avoid delays between 
// the two RDMSRs (for example, interrupts).
MCNT = RDMSR(IA32_MPERF);
ACNT = RDMSR(IA32_APERF);

// PercentPerformance indicates the percentage of the processor
// that is in use. The calculation is based on the PercentBusy, 
// that is the percentage of processor time not idle and the P-state
// hardware coordinated feedback using the ACNT/MCNT ratio.
// Note that both values need to be calculated over the same 

Figure 14-1.  IA32_MPERF MSR and IA32_APERF MSR for P-state Coordination

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0

IA32_MPERF (Addr: E7H)

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0

IA32_APERF (Addr: E8H)