Vol. 3D INDEX-1
INDEX
Numerics
16-bit code, mixing with 32-bit code
,
32-bit code, mixing with 16-bit code
,
32-bit physical addressing
overview
,
36-bit physical addressing
overview
,
64-bit mode
call gates
,
code segment descriptors
,
control registers
CR8 register
,
D flag
,
debug registers
,
descriptors
,
,
DPL field
exception handling
,
external interrupts
,
fast system calls
,
GDTR register
,
GP faults, causes of
,
IDTR register
initialization process
interrupt and trap gates
interrupt controller
interrupt descriptors
interrupt handling
interrupt stack table
,
IRET instruction
,
L flag
,
logical address translation
MOV CRn
null segment checking
paging
,
reading counters
,
reading & writing MSRs
,
registers and mode changes
,
RFLAGS register
segment descriptor tables
,
segment loading instructions
segments
,
stack switching
,
SYSCALL and SYSRET
,
,
SYSENTER and SYSEXIT
,
system registers
task gate
,
task priority
,
task register
,
TSS
stack pointers
,
See also: IA-32e mode, compatibility mode
8086
emulation, support for
processor, exceptions and interrupts
8086/8088 processor
8087 math coprocessor
82489DX
Local APIC and I/O APICs
A
A20M# signal
,
,
Aborts
description of
,
restarting a program or task after
,
AC (alignment check) flag, EFLAGS register
,
,
Access rights
checking
checking caller privileges
description of
invalid values
,
ADC instruction
ADD instruction
Address
size prefix
,
space, of task
Address translation
in real-address mode
logical to linear
,
overview
Addressing, segments
Advanced power management
C-state and Sub C-state
MWAIT extensions
,
Advanced programmable interrupt controller (see I/O APIC or Local APIC)
Alignment
check exception
,
,
,
checking
,
AM (alignment mask) flag
CR0 control register
,
AND instruction
,
APIC
,
APIC bus
arbitration mechanism and protocol
bus message format
,
diagram of
,
EOI message format
,
,
nonfocused lowest priority message
,
short message format
,
SMI message
status cycles
structure of
,
See also
APIC flag, CPUID instruction
,
APIC ID
APIC (see I/O APIC or Local APIC)
ARPL instruction
,
not supported in 64-bit mode
,
Atomic operations
automatic bus locking
effects of a locked operation on internal processor caches
guaranteed, description of
overview of
,
,
software-controlled bus locking
At-retirement
counting
,
,
events
,
,
,
Auto HALT restart
field, SMM
SMM
,
Automatic bus locking
,
Automatic thermal monitoring mechanism
B
B (busy) flag
TSS descriptor
,
,
B (default stack size) flag
segment descriptor
,
B0-B3 (BP condition detected) flags
DR6 register
Backlink (see Previous task link)
Base address fields, segment descriptor
BD (debug register access detected) flag, DR6 register
,