6-38 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

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If the PAE and/or PSE flag in control register CR4 is set and the processor detects any reserved bits in a page-
directory-pointer-table entry set to 1. These bits are checked during a write to control registers CR0, CR3, or 
CR4 that causes a reloading of the page-directory-pointer-table entry.

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Attempting to write a non-zero value into the reserved bits of the MXCSR register.

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Executing an SSE/SSE2/SSE3 instruction that attempts to access a 128-bit memory location that is not aligned 
on a 16-byte boundary when the instruction requires 16-byte alignment. This condition also applies to the stack 
segment.

A program or task can be restarted following any general-protection exception. If the exception occurs while 
attempting to call an interrupt handler, the interrupted program can be restartable, but the interrupt may be lost.

Exception Error Code

The processor pushes an error code onto the exception handler's stack. If the fault condition was detected while 
loading a segment descriptor, the error code contains a segment selector to or IDT vector number for the 
descriptor; otherwise, the error code is 0. The source of the selector in an error code may be any of the following:

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An operand of the instruction.

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A selector from a gate which is the operand of the instruction.

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A selector from a TSS involved in a task switch.

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IDT vector number.

Saved Instruction Pointer

The saved contents of CS and EIP registers point to the instruction that generated the exception.

Program State Change

In general, a program-state change does not accompany a general-protection exception, because the invalid 
instruction or operation is not executed. An exception handler can be designed to correct all of the conditions that 
cause general-protection exceptions and restart the program or task without any loss of program continuity.
If a general-protection exception occurs during a task switch, it can occur before or after the commit-to-new-task 
point (see Section 7.3, “Task Switching”). If it occurs before the commit point, no program state change occurs. If 
it occurs after the commit point, the processor will load all the state information from the new TSS (without 
performing any additional limit, present, or type checks) before it generates the exception. The general-protection 
exception handler should thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, 
and GS registers without causing another exception. (See the Program State Change description for “Interrupt 
10—Invalid TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.)

General Protection Exception in 64-bit Mode

The following conditions cause general-protection exceptions in 64-bit mode:

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If the memory address is in a non-canonical form.

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If a segment descriptor memory address is in non-canonical form.

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If the target offset in a destination operand of a call or jmp is in a non-canonical form.

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If a code segment or 64-bit call gate overlaps non-canonical space.

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If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the L-bit set and the 
D-bit clear.

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If the EFLAGS.NT bit is set in IRET.

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If the stack segment selector of IRET is null when going back to compatibility mode.

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If the stack segment selector of IRET is null going back to CPL3 and 64-bit mode.

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If a null stack segment selector RPL of IRET is not equal to CPL going back to non-CPL3 and 64-bit mode.

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If the proposed new code segment descriptor of IRET has both the D-bit and the L-bit set.