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Vol. 3D INDEX-15

INDEX

combining segment & page-level

5-29

disabling

5-1

enabling

5-1

flags used for page-level protection

5-2

5-3

flags used for segment-level protection

5-2

IA-32e mode

5-3

of exception, interrupt-handler procedures

6-13

overview of

5-1

page level

5-1

5-27

5-28

5-30

page level, overriding

5-29

page-level protection flags

5-28

read/write, page level

5-28

segment level

5-1

user/supervisor type

5-28

Protection rings

5-8

PSE (page size extension) flag

CR4 control register

2-17

11-20

22-17

22-18

PSE-36 page size extension

3-6

Pseudo-functions

VMfail

30-2

VMfailInvalid

30-2

VMfailValid

30-2

VMsucceed

30-2

Pseudo-infinity

22-9

Pseudo-NaN

22-9

Pseudo-zero

22-9

P-state

14-1

PUSH instruction

22-6

PUSHF instruction

6-7

22-6

PVI (protected-mode virtual interrupts) flag

CR4 control register

2-11

2-17

22-17

PWT pin (Pentium processor)

11-13

PWT (page-level write-through) flag

CR3 control register

2-16

11-13

22-17

22-29

page-directory entries

9-7

11-13

11-33

page-table entries

9-7

11-33

22-30

Q

QNaN, compatibility, IA-32 processors

22-8

R

RDMSR instruction

2-19

2-20

2-25

5-24

17-34

17-39

17-41

18-87

18-116

18-117

18-118

22-4

22-35

25-4

25-8

RDPMC instruction

2-24

5-24

18-86

18-116

18-117

22-4

22-17

22-36

25-4

in 64-bit mode

2-25

RDTSC instruction

2-24

5-24

17-41

22-4

25-4

25-9

in 64-bit mode

2-25

reading sensors

14-25

Read/write

protection, page level

5-28

rights, checking

5-25

Real-address mode

8086 emulation

20-1

address translation in

20-2

description of

20-1

exceptions and interrupts

20-6

IDT initialization

9-8

IDT, changing base and limit of

20-5

IDT, structure of

20-5

IDT, use of

20-4

initialization

9-8

instructions supported

20-3

interrupt and exception handling

20-4

interrupts

20-6

introduction to

2-7

mode switching

9-13

native 16-bit mode

21-1

overview of

20-1

registers supported

20-3

switching to

9-14

Recursive task switching

7-13

Related literature

1-9

Replay events

19-196

Requested privilege level (see RPL)

Reserved bits

1-6

22-2

RESET# pin

6-3

22-15

RESET# signal

2-24

Resolution in degrees

14-26

Restarting program or task, following an exception or interrupt

6-5

Restricting addressable domain

5-28

RET instruction

5-10

5-20

21-6

Returning

from a called procedure

5-20

from an interrupt or exception handler

6-13

RF (resume) flag

EFLAGS register

2-10

6-7

RPL

description of

3-8

5-8

field, segment selector

5-2

RSM instruction

2-24

8-17

22-5

25-4

34-1

34-2

34-3

34-13

34-15

34-18

RsvdZ

10-39

R/S# pin

6-3

R/W (read/write) flag

page-directory entry

5-1

5-2

5-28

page-table entry

5-1

5-2

5-28

R/W0-R/W3 (read/write) fields

DR7 register

17-4

22-19

S

S (descriptor type) flag

segment descriptor

3-11

3-12

5-2

5-5

SBB instruction

8-3

Segment descriptors

access rights

5-24

access rights, invalid values

22-18

automatic bus locking while updating

8-3

base address fields

3-10

code type

5-2

data type

5-2

description of

2-4

3-9

DPL (descriptor privilege level) field

3-11

5-2

D/B (default operation size/default stack pointer size and/or upper 

bound) flag

3-11

5-4

E (expansion direction) flag

5-2

5-4

G (granularity) flag

3-11

5-2

5-4

limit field

5-2

5-4

loading

22-19

P (segment-present) flag

3-11

S (descriptor type) flag

3-11

3-12

5-2

5-5

segment limit field

3-10

system type

5-2

tables

3-14

TSS descriptor

7-5

7-6

type field

3-10

3-12

5-2

5-5

type field, encoding

3-14

when P (segment-present) flag is clear

3-11

Segment limit

checking

2-22

field, segment descriptor

3-10

Segment not present exception (#NP)

3-11

Segment registers

description of

3-8

IA-32e mode

3-9

saved in TSS

7-4

Segment selectors

description of

3-7

index field

3-7

null

5-6

null in 64-bit mode

5-6