Vol. 3A
xlix
CONTENTS
PAGE
Table 35-8.
Specific MSRs Supported by Intel® Atom™ Processors with CPUID Signature 06_37H, 06_4AH, 06_5AH, 06_5DH35-80
Table 35-9.
Specific MSRs Supported by Intel® Atom™ Processor E3000 Series with CPUID Signature 06_37H . . . . . . . . . . . . . 35-82
Table 35-10.
Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH . . . . . . . . . . . . . 35-82
Table 35-11.
MSRs in Intel Atom Processors Based on the Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-84
Table 35-12.
MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . 35-86
Table 35-13.
MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-107
Table 35-14.
Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-124
Table 35-15.
Additional MSRs in Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-126
Table 35-16.
Additional MSRs Supported by Intel Processors
(Based on Intel® Microarchitecture Code Name Westmere)35-140
Table 35-17.
Additional MSRs Supported by Intel® Xeon® Processor E7 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-141
Table 35-18.
MSRs Supported by Intel® Processors
based on Intel® microarchitecture code name Sandy Bridge35-143
Table 35-19.
MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge)35-162
Table 35-20.
Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-163
Table 35-21.
Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) . . .35-166
Table 35-22.
Uncore PMU MSRs in Intel® Xeon® Processor E5 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-169
Table 35-23.
Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name Ivy
Bridge)35-172
Table 35-24.
MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture). .35-176
Table 35-25.
Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family with DisplayFamily_DisplayModel Signature 06_3EH
35-183
Table 35-26.
Uncore PMU MSRs in Intel® Xeon® Processor E5 v2 and E7 v2 Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-186
Table 35-27.
Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures. . . . . . . . . . . . .35-188
Table 35-28.
MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) . . . . . . . . . . . . . . . . . . . . .35-193
Table 35-29.
Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with DisplayFamily_DisplayModel
Signature 06_45H35-204
Table 35-30.
Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-206
Table 35-31.
Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-215
Table 35-32.
Additional MSRs Common to Processors Based the Broadwell Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-223
Table 35-33.
Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors . . . . . . . . .35-225
Table 35-34.
Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell
Microarchitecture35-227
Table 35-35.
Additional MSRs Supported by Intel® Xeon® Processor D with DisplayFamily_DisplayModel 06_56H . . . . . . . . . . .35-236
Table 35-36.
Additional MSRs Supported by Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_4FH . . . . . . . . . . . .35-238
Table 35-37.
Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake Microarchitecture . . .35-242
Table 35-38.
Uncore PMU MSRs Supported by 6th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-259
Table 35-39.
Machine Check MSRs Supported by Future Intel® Xeon® Processors with DisplayFamily_DisplayModel 06_55H 35-261
Table 35-40.
Selected MSRs Supported by Next Generation Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature
06_57H35-265
Table 35-41.
MSRs in the Pentium® 4 and Intel® Xeon® Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-278
Table 35-42.
MSRs Unique to 64-bit Intel® Xeon® Processor MP with
Up to an 8 MB L3 Cache35-302
Table 35-43.
MSRs Unique to Intel® Xeon® Processor 7100 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-303
Table 35-44.
MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV. . . . . . . . . . . . . .35-304
Table 35-45.
MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-313
Table 35-46.
MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-320
Table 35-47.
MSRs in the Pentium Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35-328
Table 36-1.
COFI Type for Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2
Table 36-2.
IP Filtering Packet Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6
Table 36-3.
ToPA Table Entry Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11
Table 36-4.
Algorithm to Manage Intel PT ToPA PMI and XSAVES/XRSTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-14
Table 36-5.
Behavior on Restricted Memory Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15
Table 36-6.
IA32_RTIT_CTL MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-16
Table 36-7.
IA32_RTIT_STATUS MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-20
Table 36-9.
IA32_RTIT_OUTPUT_MASK_PTRS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22
Table 36-8.
IA32_RTIT_OUTPUT_BASE MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22
Table 36-10.
TSX Packet Scenarios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-23
Table 36-11.
CPUID Leaf 14H Enumeration of Intel Processor Trace Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26
Table 36-12.
CPUID Leaf 14H, sub-leaf 1H Enumeration of Intel Processor Trace Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-28
Table 36-13.
Memory Layout of the Trace Configuration State Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-31
Table 36-14.
An Illustrative CYC Packet Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-33
Table 36-15.
Compound Packet Event Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-36
Table 36-16.
TNT Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-36
Table 36-17.
IP Packet Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-38
