Vol. 3C 35-303

MODEL-SPECIFIC REGISTERS (MSRS)

The MSRs listed in Table 35-43 apply to Intel

®

 Xeon

®

 Processor 7100 series. These processors can be detected by 

enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the 
presence of the third level cache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID 
instruction for more details.). The performance monitoring MSRs listed in Table 35-43 are shared between logical 
processors in the same core, but are replicated for each core.

107D0H

MSR_EFSB_DRDY0

3, 4

Shared

EFSB DRDY Event Control and Counter 

Register (R/W) 
See Section 18.17, “Performance 

Monitoring on 64-bit Intel Xeon Processor 

MP with Up to 8-MByte L3 Cache” for 

details.

107D1H

MSR_EFSB_DRDY1

3, 4

Shared

EFSB DRDY Event Control and Counter 

Register (R/W)

107D2H

MSR_IFSB_CTL6

3, 4

Shared

IFSB Latency Event Control Register 

(R/W)
See Section 18.17, “Performance 

Monitoring on 64-bit Intel Xeon Processor 

MP with Up to 8-MByte L3 Cache” for 

details.

107D3H

MSR_IFSB_CNTR7

3, 4

Shared

IFSB Latency Event Counter Register 

(R/W) 
See Section 18.17, “Performance 

Monitoring on 64-bit Intel Xeon Processor 

MP with Up to 8-MByte L3 Cache.” 

Table 35-43.  MSRs Unique to Intel® Xeon® Processor 7100 Series

Register Address

Register Name

Fields and Flags

Model Avail-

ability

Shared/

Unique

Bit Description

107CCH

MSR_EMON_L3_CTR_CTL0

6

Shared

GBUSQ Event Control and Counter 

Register (R/W)
See Section 18.17, “Performance 

Monitoring on 64-bit Intel Xeon Processor 

MP with Up to 8-MByte L3 Cache.”

107CDH

MSR_EMON_L3_CTR_CTL1

6

Shared

GBUSQ Event Control and Counter 

Register (R/W) 

107CEH

MSR_EMON_L3_CTR_CTL2

6

Shared

GSNPQ Event Control and Counter 

Register (R/W) 
See Section 18.17, “Performance 

Monitoring on 64-bit Intel Xeon Processor 

MP with Up to 8-MByte L3 Cache.”

107CFH

MSR_EMON_L3_CTR_CTL3

6

Shared

GSNPQ Event Control and Counter 

Register (R/W)

Table 35-42.  MSRs Unique to 64-bit Intel® Xeon® Processor MP with 

Up to an 8 MB L3 Cache (Contd.)

Register Address

Register Name

Fields and Flags

Model Avail-

ability

Shared/

Unique

Bit Description