Vol. 3C 35-225

MODEL-SPECIFIC REGISTERS (MSRS)

Table 35-33 lists MSRs that are specific to Intel Core M processors and 5th Generation Intel Core Processors.

0

Reserved, writes ignored.

1

ContexEn, writes ignored.

2

TriggerEn, writes ignored.

3

Reserved

4

Error (R/W)

5

Stopped

63:6

Reserved, MBZ.

572H

1394

IA32_RTIT_CR3_MATCH

THREAD

Trace Filter CR3 Match Register (R/W)

4:0

Reserved

63:5

CR3[63:5] value to match

NOTES:

1. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].

Table 35-33.  Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec

E2H

226

MSR_PKG_CST_CONFIG_
CONTROL

Core

C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-states.
See http://biosbits.org.

3:0

Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name 

(consuming the least power) for the package. The default is set as 

factory-configured package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10

9:4

Reserved

10

I/O MWAIT Redirection Enable (R/W)

Table 35-32.  Additional MSRs Common to Processors Based the Broadwell Microarchitectures

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec