35-84 Vol. 3C

MODEL-SPECIFIC REGISTERS (MSRS)

Table 35-11.   MSRs in Intel Atom Processors Based on the Airmont Microarchitecture

Address

Register Name

Scope

Bit Description

 Hex

Dec

CDH

205

MSR_FSB_FREQ

Module

Scaleable Bus Speed(RO)
This field indicates the intended scaleable bus clock speed for 

processors based on Airmont microarchitecture:

3:0

• 0000B: 083.3 MHz 

• 0001B: 100.0 MHz 

• 0010B: 133.3 MHz 

• 0011B: 116.7 MHz 

• 0100B: 080.0 MHz 

• 0101B: 093.3 MHz 

• 0110B: 090.0 MHz 

• 0111B: 088.9 MHz 

• 10sure00B: 087.5 MHz 

63:5

Reserved.

E2H

226

MSR_PKG_CST_CONFIG_

CONTROL

Module

C-State Configuration Control (R/W) 
Note: C-state values are processor specific C-state code names, 

unrelated to MWAIT extension C-state parameters or ACPI C-

States.
See http://biosbits.org.

2:0

Package C-State Limit (R/W) 
Specifies the lowest processor-specific C-state code name 

(consuming the least power). for the package. The default is set as 

factory-configured package C-state limit.
The following C-state code name encodings are supported:
000b: No limit
001b: C1 
010b: C2 
110b: C6
111b: C7 

9:3

Reserved.

10

I/O MWAIT Redirection Enable (R/W) 
When set, will map IO_read instructions sent to IO register 

specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions

14:11

Reserved.

15

CFG Lock (R/WO) 
When set, lock bits 15:0 of this register until next reset.

63:16

Reserved.

E4H

228

MSR_PMG_IO_CAPTURE_

BASE

Module

Power Management IO Redirection in C-state (R/W) 
See http://biosbits.org.

15:0

LVL_2 Base Address (R/W) 
Specifies the base address visible to software for IO redirection. If 

IO MWAIT Redirection is enabled, reads to this address will be 

consumed by the power management logic and decoded to MWAIT 

instructions. When IO port address redirection is enabled, this is the 

IO port address reported to the OS/software.