Vol. 3D INDEX-21
INDEX
overview
,
RSM instruction
VMCS pointer
,
VMX-critical state
testing for support
virtual TLBs
,
virtual-machine control structure (VMCS)
virtual-machine monitor (VMM)
vitualization of system resources
,
VM entries and exits
,
VM exits
,
VMCS pointer
,
VMM life cycle
,
VMXOFF instruction
,
VMXON instruction
,
VMXON pointer
VMXON region
,
See also:VMM, VMCS, VM entries, VM exits
VMXOFF instruction
,
VMXON instruction
,
W
WAIT/FWAIT instructions
,
WB (write back) memory type
,
,
WB (write-back) pin (Pentium processor)
,
WBINVD instruction
WB/WT# pins
,
WC buffer (see Write combining (WC) buffer)
WC (write combining)
flag, IA32_MTRRCAP MSR
memory type
,
WP (write protected) memory type
WP (write protect) flag
CR0 control register
,
Write
hit
,
Write combining (WC) buffer
,
Write-back caching
WRMSR instruction
,
,
,
,
WT (write through) memory type
,
WT# (write-through) pin (Pentium processor)
X
x2APIC ID
,
x2APIC Mode
,
,
,
x87 FPU
compatibility with IA-32 x87 FPUs and math coprocessors
configuring the x87 FPU environment
device-not-available exception
effect of MMX instructions on pending x87 floating-point exceptions
,
effects of MMX instructions on x87 FPU state
,
effects of MMX, x87 FPU, FXSAVE, and FXRSTOR instructions on x87
FPU tag word
,
error signals
initialization
instruction synchronization
register stack, aliasing with MMX registers
,
setting up for software emulation of x87 FPU functions
using TS flag to control saving of x87 FPU state
,
x87 floating-point error exception (#MF)
,
x87 FPU control word
compatibility, IA-32 processors
x87 FPU floating-point error exception (#MF)
x87 FPU status word
condition code flags
x87 FPU tag word
XADD instruction
xAPIC
,
determining lowest priority processor
,
interrupt control register
,
introduction to
message passing protocol on system bus
new features
spurious vector
using system bus
xAPIC Mode
,
,
XCHG instruction
,
,
XCR0
,
XGETBV
,
XMM registers, saving
XOR instruction
,
XSAVE
,
,
,
XSETBV
,
,
Z
ZF flag, EFLAGS register
,