Page 450

12-2 Vol. 3A

INTEL

MMX

™

TECHNOLOGY SYSTEM PROGRAMMING

When a value is written into an MMX register using an MMX instruction, the value also appears in the corresponding
floating-point register in bits 0 through 63. Likewise, when a floating-point value written into a floating-point
register by a x87 FPU, the low 64 bits of that value also appears in a the corresponding MMX register.
The execution of MMX instructions have several side effects on the x87 FPU state contained in the floating-point
registers, the x87 FPU tag word, and the x87 FPU status word. These side effects are as follows:

•

When an MMX instruction writes a value into an MMX register, at the same time, bits 64 through 79 of the corre-
sponding floating-point register are set to all 1s.

•

When an MMX instruction (other than the EMMS instruction) is executed, each of the tag fields in the x87 FPU
tag word is set to 00B (valid). (See also Section 12.2.1, “Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR
Instructions on the x87 FPU Tag Word.”)

•

When the EMMS instruction is executed, each tag field in the x87 FPU tag word is set to 11B (empty).

•

Each time an MMX instruction is executed, the TOS value is set to 000B.

Execution of MMX instructions does not affect the other bits in the x87 FPU status word (bits 0 through 10 and bits
14 and 15) or the contents of the other x87 FPU registers that comprise the x87 FPU state (the x87 FPU control
word, instruction pointer, data pointer, or opcode registers).
Table 12-2 summarizes the effects of the MMX instructions on the x87 FPU state.

Figure 12-1. Mapping of MMX Registers to Floating-Point Registers

Floating-Point Registers

64 63

x87 FPU Status Register

x87 FPU Tag

MMX Registers

TOS

MM7

MM6

MM5

MM4

MM3

MM2

MM1

MM0

TOS = 0

000