INDEX
INDEX-2 Vol. 3D
Binary numbers
,
BINIT# signal
BIOS role in microcode updates
,
Bit order
,
BOUND instruction
,
,
BOUND range exceeded exception (#BR)
,
BP0#, BP1#, BP2#, and BP3# pins
,
Branch record
branch trace message
,
IA-32e mode
,
saving
,
saving as a branch trace message
structure
structure of in BTS buffer
Branch trace message (see BTM)
Breakpoint exception (#BP)
,
Breakpoints
data breakpoint
data breakpoint exception conditions
description of
,
DR0-DR3 debug registers
,
example
exception
field recognition
,
general-detect exception condition
instruction breakpoint
instruction breakpoint exception condition
,
I/O breakpoint exception conditions
LEN0 - LEN3 (Length) fields
DR7 register
,
R/W0-R/W3 (read/write) fields
DR7 register
,
single-step exception condition
task-switch exception condition
BS (single step) flag, DR6 register
BSP flag, IA32_APIC_BASE MSR
BSWAP instruction
BT (task switch) flag, DR6 register
,
BTC instruction
,
BTF (single-step on branches) flag
DEBUGCTLMSR MSR
BTMs (branch trace messages)
description of
,
enabling
,
,
,
TR (trace message enable) flag
MSR_DEBUGCTLA MSR
,
MSR_DEBUGCTLB MSR
,
,
,
BTR instruction
,
BTS buffer
description of
,
introduction to
,
,
records in
setting up
,
structure of
BTS instruction
,
BTS (branch trace store) facilities
availability of
,
BTS_UNAVAILABLE flag,
IA32_MISC_ENABLE MSR
introduction to
,
setting up BTS buffer
,
writing an interrupt service routine for
,
BTS_UNAVAILABLE
Built-in self-test (BIST)
description of
,
performing
,
Bus
errors detected with MCA
,
hold
,
locking
,
Byte order
,
C
C (conforming) flag, segment descriptor
C1 flag, x87 FPU status word
,
C2 flag, x87 FPU status word
,
Cache control
adaptive mode, L1 Data Cache
,
cache management instructions
,
cache mechanisms in IA-32 processors
,
caching terminology
CD flag, CR0 control register
,
choosing a memory type
CPUID feature flag
,
flags and fields
flushing TLBs
G (global) flag
page-directory entries
,
page-table entries
internal caches
,
MemTypeGet() function
MemTypeSet() function
,
MESI protocol
,
methods of caching available
,
MTRR initialization
,
MTRR precedences
,
MTRRs, description of
multiple-processor considerations
NW flag, CR0 control register
,
,
operating modes
,
overview of
,
page attribute table (PAT)
PCD flag
CR3 control register
,
page-directory entries
,
,
page-table entries
PGE (page global enable) flag, CR4 control register
precedence of controls
,
preventing caching
,
protocol
PWT flag
CR3 control register
,
page-directory entries
,
page-table entries
remapping memory types
setting up memory ranges with MTRRs
shared mode, L1 Data Cache
variable-range MTRRs
Caches
cache hit
cache line
cache line fill
,
cache write hit
description of
effects of a locked operation on internal processor caches
enabling
management, instructions
,
Caching
cache control protocol
,
cache line
cache management instructions
,
cache mechanisms in IA-32 processors
,
caching terminology
choosing a memory type
flushing TLBs
implicit caching
internal caches
,
L1 (level 1) cache
L2 (level 2) cache
L3 (level 3) cache
methods of caching available
,
MTRRs, description of
operating modes
,
overview of
,