Vol. 3D INDEX-17
INDEX
SIMD Floating-point exception (#XM)
,
using TS flag to control saving state
SSE2 feature flag
CPUID instruction
,
SSE3 extensions
checking for with CPUID
,
CPUID feature flag
EM flag
emulation of
example verifying SS3 support
,
facilities for automatic saving of state
,
initialization
introduction of into the IA-32 architecture
providing exception handlers for
,
providing operating system support for
saving and restoring state
saving state on task, context switches
using TS flag to control saving of state
,
SSE3 feature flag
CPUID instruction
,
Stack fault exception (#SS)
Stack fault, x87 FPU
,
Stack pointers
privilege level 0, 1, and 2 stacks
,
size of
,
Stack segments
paging of
privilege level check when loading SS register
size of stack pointer
,
Stack switching
exceptions/interrupts when switching stacks
IA-32e mode
,
inter-privilege level calls
,
Stack-fault exception (#SS)
,
Stacks
error code pushes
,
faults
for privilege levels 0, 1, and 2
interlevel RET/IRET
from a 16-bit interrupt or call gate
,
interrupt stack table, 64-bit mode
management of control transfers for
16- and 32-bit procedure calls
,
operation on pushes and pops
pointers to in TSS
stack switching
,
usage on call to exception
or interrupt handler
Stepping information, following processor initialization or reset
,
STI instruction
,
Store buffer
caching terminology
characteristics of
,
description of
,
in IA-32 processors
location of
,
operation of
,
STPCLK# pin
STR instruction
,
Strong uncached (UC) memory type
description of
,
effect on memory ordering
use of
,
,
Sub C-state
,
SUB instruction
,
Supervisor mode
description of
,
U/S (user/supervisor) flag
SVR (spurious-interrupt vector register), local APIC
SWAPGS instruction
SYSCALL instruction
,
,
SYSENTER instruction
,
,
,
SYSENTER_CS_MSR
,
SYSENTER_EIP_MSR
SYSENTER_ESP_MSR
,
SYSEXIT instruction
,
SYSRET instruction
,
System
architecture
,
data structures
,
instructions
registers in IA-32e mode
registers, introduction to
,
segment descriptor, layout of
segments, paging of
,
System programming
MMX technology
virtualization of resources
,
System-management mode (see SMM)
T
T (debug trap) flag, TSS
,
Task gates
descriptor
,
executing a task
handling a virtual-8086 mode interrupt or exception through
IA-32e mode
in IDT
,
introduction for IA-32e
,
introduction to
,
layout of
referencing of TSS descriptor
,
Task management
,
data structures
,
mechanism, description of
Task register
description of
,
,
IA-32e mode
initializing
introduction to
Task switching
description of
exception condition
operation
preventing recursive task switching
,
saving MMX state on
,
saving SSE/SSE2/SSE3 state
on task or context switches
,
T (debug trap) flag
,
Tasks
address space
description of
exception-handler task
executing
,
Intel 286 processor tasks
,
interrupt-handler task
interrupts and exceptions
linking
logical address space
,
management
mapping linear and physical address space
restart following an exception or interrupt
,
state (context)
,
structure
,
switching
task management data structures
,
TF (trap) flag, EFLAGS register
,
,
,
,
,
,
Thermal monitoring
advanced power management
,
automatic
automatic thermal monitoring
catastrophic shutdown detector
,