Vol. 3D INDEX-11
INDEX
M
Machine check architecture
VMX considerations
,
Machine-check architecture
availability of MCA and exception
,
compatibility with Pentium processor
compound error codes
CPUID flags
,
error codes
error-reporting bank registers
error-reporting MSRs
extended machine check state MSRs
,
external bus errors
,
first introduced
,
global MSRs
,
initialization of
introduction of in IA-32 processors
,
logging correctable errors
,
,
machine-check exception handler
,
machine-check exception (#MC)
,
MSRs
,
overview of MCA
,
Pentium processor exception handling
,
Pentium processor style error reporting
,
simple error codes
VMX considerations
,
writing machine-check software
Machine-check exception (#MC)
,
,
Mapping of shared resources
Maskable hardware interrupts
description of
,
handling with virtual interrupt mechanism
masking
,
MCA flag, CPUID instruction
,
MCE flag, CPUID instruction
MCE (machine-check enable) flag
CR4 control register
,
MDA (message destination address)
local APIC
Memory
Memory management
introduction to
,
overview
,
paging
,
,
registers
segments
,
,
virtualization of
Memory ordering
in IA-32 processors
overview
,
processor ordering
,
strengthening or weakening
,
write ordering
,
Memory type range registers (see MTRRs)
Memory types
caching methods, defined
choosing
,
MTRR types
,
selecting for Pentium III and Pentium 4 processors
,
selecting for Pentium Pro and Pentium II processors
UC (strong uncacheable)
,
UC- (uncacheable)
,
WB (write back)
,
WC (write combining)
WP (write protected)
writing values across pages with different memory types
,
WT (write through)
MemTypeGet() function
MemTypeSet() function
MESI cache protocol
,
Message address register
,
Message data register format
,
Message signalled interrupts
message address register
,
message data register format
,
MFENCE instruction
,
,
Microcode update facilities
authenticating an update
BIOS responsibilities
calling program responsibilities
checksum
extended signature table
,
family 0FH processors
,
field definitions
format of update
,
function 00H presence test
function 01H write microcode update data
function 02H microcode update control
function 03H read microcode update data
general description
,
HT Technology
,
INT 15H-based interface
,
overview
process description
,
processor identification
,
processor signature
return codes
update loader
,
update signature and verification
,
update specifications
VMX non-root operation
,
VMX support
early loading
late loading
virtualization issues
Mixing 16-bit and 32-bit code
in IA-32 processors
,
overview
MMX technology
debugging MMX code
effect of MMX instructions on pending x87 floating-point exceptions
,
emulation of the MMX instruction set
exceptions that can occur when executing MMX instructions
,
introduction of into the IA-32 architecture
,
register aliasing
state
state, saving and restoring
system programming
,
task or context switches
using TS flag to control saving of MMX state
Mode switching
example
,
real-address and protected mode
,
to SMM
Model and stepping information, following processor initialization or reset
,
Model-specific registers (see MSRs)
Modes of operation (see Operating modes)
MONITOR instruction
,
MOV instruction
,
MOV (control registers) instructions
,
,
MOV (debug registers) instructions
,
,
MOVNTDQ instruction
,
,
MOVNTI instruction
,
,
MOVNTPD instruction
,
,
MOVNTPS instruction
,
,
MOVNTQ instruction
MP (monitor coprocessor) flag
CR0 control register
,
,
,
,
MSR
Model Specific Register
,
MSRs
architectural
,