INDEX
INDEX-6 Vol. 3D
FPREM1 instruction
,
FPTAN instruction
,
Front_end events
,
FRSTOR instruction
,
FSAVE instruction
,
FSAVE/FNSAVE instructions
,
FSCALE instruction
FSIN instruction
,
FSINCOS instruction
FSQRT instruction
FSTENV instruction
,
FSTENV/FNSTENV instructions
FTAN instruction
FUCOM instruction
FUCOMI instruction
FUCOMIP instruction
,
FUCOMP instruction
FUCOMPP instruction
,
FWAIT instruction
,
FXAM instruction
,
,
FXRSTOR instruction
,
,
,
,
FXSAVE instruction
,
FXSR feature flag, CPUID instruction
,
FXTRACT instruction
,
G
G (global) flag
page-directory entries
page-table entries
,
G (granularity) flag
segment descriptor
,
,
,
G0-G3 (global breakpoint enable) flags
DR7 register
,
Gate descriptors
call gates
,
description of
,
IA-32e mode
,
Gates
IA-32e mode
,
GD (general detect enable) flag
DR7 register
,
GDT
description of
,
,
IA-32e mode
,
index field of segment selector
,
initializing
,
paging of
pointers to exception/interrupt handlers
segment descriptors in
selecting with TI flag of segment selector
,
task switching
task-gate descriptor
,
TSS descriptors
,
use in address translation
,
GDTR register
description of
,
,
IA-32e mode
,
limit
,
loading during initialization
,
storing
,
GE (global exact breakpoint enable) flag
DR7 register
,
General-detect exception condition
General-protection exception (#GP)
,
,
,
,
,
,
General-purpose registers, saved in TSS
Global control MSRs
Global descriptor table register (see GDTR)
Global descriptor table (see GDT)
H
HALT state
relationship to SMI interrupt
,
Hardware reset
description of
processor state after reset
state of MTRRs following
,
value of SMBASE following
,
Hexadecimal numbers
high-temperature interrupt enable bit
,
,
HITM# line
HLT instruction
,
,
,
,
Hyper-Threading Technology
architectural state of a logical processor
architecture description
,
caches
,
counting clockticks
,
debug registers
description of
,
detecting
,
,
executing multiple threads
execution-based timing loops
,
external signal compatibility
halting logical processors
,
handling interrupts
HLT instruction
,
IA32_MISC_ENABLE MSR
,
initializing IA-32 processors with
,
introduction of into the IA-32 architecture
,
local a
local APIC
functionality in logical processor
,
logical processors, identifying
,
machine check architecture
managing idle and blocked conditions
,
mapping resources
memory ordering
,
microcode update resources
,
,
MP systems
MTRRs
,
multi-threading feature flag
,
multi-threading support
,
PAT
,
PAUSE instruction
,
performance monitoring
,
performance monitoring counters
,
placement of locks and semaphores
required operating system support
scheduling multiple threads
self modifying code
serializing instructions
,
spin-wait loops
PAUSE instructions in
,
thermal monitor
,
TLBs
,
I
IA-32 Intel architecture
compatibility
processors
,
IA32e mode
registers and mode changes
IA-32e mode
call gates
code segment descriptor
D flag
data structures and initialization
debug registers
descriptors
DPL field
,