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Vol. 3D INDEX-19

INDEX

USR (user mode) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family 

processors)

18-3

18-7

18-8

18-9

18-10

18-18

18-19

18-41

18-43

18-51

18-52

18-70

18-72

18-73

18-116

U/S (user/supervisor) flag

page-directory entry

5-1

5-2

5-28

page-table entries

20-8

page-table entry

5-1

5-2

5-28

V

V (valid) flag

IA32_MTRR_PHYSMASKn MTRR

11-24

11-26

Variable-range MTRRs, description of

11-23

11-25

VCNT (variable range registers count) field, IA32_MTRRCAP MSR

11-22

Vectors

exceptions

6-1

interrupts

6-1

VERR instruction

2-23

5-25

VERW instruction

2-23

5-25

VIF (virtual interrupt) flag

EFLAGS register

2-11

22-5

22-6

VIP (virtual interrupt pending) flag

EFLAGS register

2-11

22-5

22-6

Virtual memory

2-6

3-1

3-2

Virtual-8086 mode

8086 emulation

20-1

description of

20-5

emulating 8086 operating system calls

20-18

enabling

20-6

entering

20-8

exception and interrupt handling overview

20-11

exceptions and interrupts, handling through a task gate

20-14

exceptions and interrupts, handling through a trap or interrupt gate

20-12

handling exceptions and interrupts through a task gate

20-14

interrupts

20-6

introduction to

2-7

IOPL sensitive instructions

20-10

I/O-port-mapped I/O

20-11

leaving

20-9

memory mapped I/O

20-11

native 16-bit mode

21-1

overview of

20-1

paging of virtual-8086 tasks

20-7

protection within a virtual-8086 task

20-8

special I/O buffers

20-11

structure of a virtual-8086 task

20-7

virtual I/O

20-10

VM flag, EFLAGS register

2-10

Virtual-8086 tasks

paging of

20-7

protection within

20-8

structure of

20-7

Virtualization

debugging facilities

32-1

interrupt vector space

33-3

memory

32-2

microcode update facilities

32-8

operating modes

32-2

page faults

32-5

system resources

32-1

TLBs

32-3

VM

OSs and application software

31-1

programming considerations

31-1

VM entries

basic VM-entry checks

26-2

checking guest state

control registers

26-8

debug registers

26-8

descriptor-table registers

26-11

MSRs

26-8

non-register state

26-12

RIP and RFLAGS

26-11

segment registers

26-9

checks on controls, host-state area

26-2

registers and MSRs

26-6

segment and descriptor-table registers

26-7

VMX control checks

26-2

exit-reason numbers

C-1

loading guest state

26-14

control and debug registers, MSRs

26-15

RIP, RSP, RFLAGS

26-16

segment & descriptor-table registers

26-16

loading MSRs

26-17

failure cases

26-17

VM-entry MSR-load area

26-17

overview of failure conditions

26-1

overview of steps

26-1

VMLAUNCH and VMRESUME

26-1

See also: VMCS, VMM, VM exits

VM exits

architectural state

existing before exit

27-1

updating state before exit

27-1

basic VM-exit information fields

27-4

basic exit reasons

27-4

exit qualification

27-4

exception bitmap

27-1

exceptions (faults, traps, and aborts)

25-5

exit-reason numbers

C-1

external interrupts

25-5

handling of exits due to exceptions

31-8

IA-32 faults and VM exits

25-1

INITs

25-5

instructions that cause:

conditional exits

25-2

unconditional exits

25-2

interrupt-window exiting

25-6

non-maskable interrupts (NMIs)

25-5

page faults

25-5

reflecting exceptions to guest

31-8

resuming guest after exception handling

31-9

start-up IPIs (SIPIs)

25-5

task switches

25-5

See also: VMCS, VMM, VM entries

VM (virtual-8086 mode) flag

EFLAGS register

2-8

2-10

VMCALL instruction

30-1

VMCLEAR instruction

30-1

31-7

VMCS

error numbers

30-29

field encodings

1-6

B-1

16-bit guest-state fields

B-1

16-bit host-state fields

B-2

32-bit control fields

B-1

B-6

32-bit guest-state fields

B-7

32-bit read-only data fields

B-7

64-bit control fields

B-2

64-bit guest-state fields

B-4

B-5

natural-width control fields

B-8

natural-width guest-state fields

B-9

natural-width host-state fields

B-10

natural-width read-only data fields

B-9

format of VMCS region

24-2

guest-state area

24-3

24-4

guest non-register state

24-5

guest register state

24-4

host-state area

24-3

24-8

introduction

24-1

migrating between processors

24-24

software access to

24-24

VMCS data

24-2

25-16

VMCS pointer

24-1

31-2