Vol. 3B 18-19
PERFORMANCE MONITORING
MSR_PERF_GLOBAL_STATUS MSR provides single-bit status used by software to query the overflow condition of
each performance counter. MSR_PERF_GLOBAL_STATUS[bit 62] indicates overflow conditions of the DS area data
buffer. MSR_PERF_GLOBAL_STATUS[bit 63] provides a CondChgd bit to indicate changes to the state of perfor-
mance monitoring hardware (see Figure 18-16). A value of 1 in bits 34:32, 1, 0 indicates an overflow condition has
occurred in the associated counter.
When a performance counter is configured for PEBS, an overflow condition in the counter will arm PEBS. On the
subsequent event following overflow, the processor will generate a PEBS event. On a PEBS event, the processor will
perform bounds checks based on the parameters defined in the DS Save Area (see Section 17.4.9). Upon
successful bounds checks, the processor will store the data record in the defined buffer area, clear the counter
overflow status, and reload the counter. If the bounds checks fail, the PEBS will be skipped entirely. In the event
that the PEBS buffer fills up, the processor will set the OvfBuffer bit in MSR_PERF_GLOBAL_STATUS.
MSR_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow the indicators for general-purpose or fixed-
function counters via a single WRMSR (see Figure 18-17). Clear overflow indications when:
•
Setting up new values in the event select and/or UMASK field for counting or interrupt-based event sampling.
•
Reloading counter values to continue collecting next sample.
•
Disabling event counting or interrupt-based event sampling.
Figure 18-16. Layout of MSR_PERF_GLOBAL_STATUS MSR
Figure 18-17. Layout of MSR_PERF_GLOBAL_OVF_CTRL MSR
62
FIXED_CTR2 Overflow
FIXED_CTR1 Overflow
FIXED_CTR0 Overflow
PMC1 Overflow
2 1 0
PMC0 Overflow
31
32
33
34
35
Reserved
63
CondChgd
OvfBuffer
62
FIXED_CTR2 ClrOverflow
FIXED_CTR1 ClrOverflow
FIXED_CTR0 ClrOverflow
PMC1 ClrOverflow
2 1 0
PMC0 ClrOverflow
31
32
33
34
35
Reserved
63
ClrCondChgd
ClrOvfBuffer