Page 1969

Vol. 3D INDEX-5

INDEX

Error code

architectural MCA

decoding IA32_MCi_STATUS

exception, description of

external bus

memory hierarchy

pushing on stack

watchdog timer

Error numbers

VM-instruction error field

30-29

Error signals

22-10

Error-reporting bank registers

15-2

ERROR#

input

22-15

output

22-15

ES0 and ES1 (event select) fields, CESR MSR (Pentium processor)

18-119

ESR

Error Status Register

10-39

ET (extension type) flag, CR0 control register

2-15

22-7

Event select field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family

processors)

18-3

18-17

18-116

Events

at-retirement

18-95

at-retirement (Pentium 4 processor)

18-84

non-retirement (Pentium 4 processor)

P6 family processors

Pentium processor

Exception handler

calling

6-11

defined

6-1

flag usage by handler procedure

6-14

machine-check exception handler

15-27

machine-check exceptions (#MC)

15-27

machine-error logging utility

15-27

procedures

6-11

protection of handler procedures

6-13

task

6-14

7-2

Exceptions

alignment check

22-11

classifications

6-4

compound error codes

15-20

conditions checked during a task switch

7-11

coprocessor segment overrun

description of

device not available

double fault

error code

exception bitmap

execute-disable bit

floating-point error

general protection

handler mechanism

handler procedures

handling

handling in real-address mode

20-4

handling in SMM

34-10

handling in virtual-8086 mode

20-11

handling through a task gate in virtual-8086 mode

20-14

handling through a trap or interrupt gate in virtual-8086 mode

20-12

IA-32e mode

2-5

IDT

6-9

initializing for protected-mode operation

9-10

invalid-opcode

22-5

masking debug exceptions

6-7

masking when switching stack segments

MCA error codes

MMX instructions

notation

overview of

priorities among simultaneous exceptions and interrupts

6-8

priority of

22-21

priority of, x87 FPU exceptions

22-10

reference information on all exceptions

6-19

reference information, 64-bit mode

6-16

restarting a task or program

segment not present

simple error codes

sources of

summary of

vectors

Executable

Execute-disable bit capability

conditions for

5-30

CPUID flag

5-30

detecting and enabling

5-30

exception handling

5-32

page-fault exceptions

6-40

protection matrix for IA-32e mode

5-31

protection matrix for legacy modes

5-31

reserved bit checking

5-31

Execution events

19-196

Exit-reason numbers

VM entries & exits

C-1

Expand-down data segment type

3-11

Extended signature table

9-31

extended signature table

9-31

External bus errors, detected with machine-check architecture

F2XM1 instruction

Family 06H

Family 0FH

microcode update facilities

9-28

Faults

description of

6-5

restarting a program or task after

FCMOVcc instructions

FCOMI instruction

FCOMIP instruction

FCOS instruction

FDISI instruction (obsolete)

22-14

FDIV instruction

22-11

22-12

FE (fixed MTRRs enabled) flag, IA32_MTRR_DEF_TYPE MSR

11-23

Feature

determination, of processor

22-2

information, processor

22-2

FENI instruction (obsolete)

22-14

FINIT/FNINIT instructions

22-7

22-15

FIX (fixed range registers supported) flag, IA32_MTRRCAPMSR

11-22

Fixed-range MTRRs

description of

11-23

Flat segmentation model

FLD instruction

FLDENV instruction

FLDL2E instruction

FLDL2T instruction

FLDLG2 instruction

FLDLN2 instruction

FLDPI instruction

Floating-point error exception (#MF)

22-11

Floating-point exceptions

denormal operand exception (#D)

22-9

invalid operation (#I)

22-13

numeric overflow (#O)

22-9

numeric underflow (#U)

22-10

saved CS and EIP values

22-10

FLUSH# pin

6-3

FNSAVE instruction

12-4

Focus processor, local APIC

10-25

FORCEPR# log

14-25

14-29

FORCPR# interrupt enable bit

FPATAN instruction

FPREM instruction