Vol. 3D INDEX-3
INDEX
self-modifying code, effect on
snooping
,
store buffer
TLBs
UC (strong uncacheable) memory type
,
UC- (uncacheable) memory type
WB (write back) memory type
,
WC (write combining) memory type
WP (write protected) memory type
write-back caching
,
WT (write through) memory type
,
Call gates
16-bit, interlevel return from
accessing a code segment through
description of
,
for 16-bit and 32-bit code modules
IA-32e mode
,
introduction to
,
mechanism
,
privilege level checking rules
CALL instruction
,
,
,
Caller access privileges, checking
Calls
16 and 32-bit code segments
controlling operand-size attribute
,
returning from
,
Capability MSRs
Catastrophic shutdown detector
Thermal monitoring
catastrophic shutdown detector
,
catastrophic shutdown detector
,
CC0 and CC1 (counter control) fields, CESR MSR (Pentium processor)
,
CD (cache disable) flag, CR0 control register
,
,
,
,
CESR (control and event select) MSR (Pentium processor)
CLFLSH feature flag, CPUID instruction
,
CLFLUSH instruction
,
CLI instruction
,
Clocks
counting processor clocks
Hyper-Threading Technology
,
nominal CPI
non-halted clockticks
non-halted CPI
,
non-sleep Clockticks
time stamp counter
CLTS instruction
,
,
Cluster model, local APIC
,
CMOVcc instructions
,
CMPXCHG instruction
CMPXCHG8B instruction
Code modules
16 bit vs. 32 bit
,
mixing 16-bit and 32-bit code
sharing data, mixed-size code segs
,
transferring control, mixed-size code segs
,
Code segments
accessing data in
accessing through a call gate
description of
,
descriptor format
descriptor layout
direct calls or jumps to
paging of
pointer size
,
privilege level checks
transferring control between code segs
Compatibility
IA-32 architecture
software
,
Compatibility mode
code segment descriptor
code segment descriptors
control registers
CS.L and CS.D
debug registers
EFLAGS register
,
exception handling
gates
,
GDTR register
,
global and local descriptor tables
,
IDTR register
,
interrupt handling
,
L flag
,
memory management
,
operation
segment loading instructions
,
segments
switching to
,
SYSCALL and SYSRET
SYSENTER and SYSEXIT
system flags
system registers
,
task register
See also: 64-bit mode, IA-32e mode
Condition code flags, x87 FPU status word
compatibility information
Conforming code segments
accessing
C (conforming) flag
description of
Context, task (see Task state)
Control registers
64-bit mode
,
CR0
CR1 (reserved)
CR2
CR3 (PDBR)
,
CR4
description of
introduction to
VMX operation
Coprocessor segment
overrun exception
,
Counter mask field
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors)
,
CPL
description of
field, CS segment selector
,
CPUID instruction
availability
,
control register flags
,
detecting features
serializing instructions
,
syntax for data
CR0 control register
,
description of
introduction to
state following processor reset
CR1 control register (reserved)
,
CR2 control register
description of
introduction to
CR3 control register (PDBR)
associated with a task
description of
in TSS
introduction to
loading during initialization
memory management
,
page directory base address
,