Vol. 3A
xlvii
CONTENTS
PAGE
Table 18-66.
Effect of Logical Processor and CPL Qualification
for Logical-Processor-Specific (TS) Events18-102
Table 18-67.
Effect of Logical Processor and CPL Qualification
for Non-logical-Processor-specific (TI) Events18-103
Table 19-1.
Architectural Performance Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Table 19-2.
Fixed-Function Performance Counter and Pre-defined Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Table 19-3.
Non-Architectural Performance Events of the Processor Core Supported by Skylake Microarchitecture . . . . . . . . . 19-3
Table 19-4.
Intel® TSX Performance Event Addendum in Processors based on Skylake Microarchitecture . . . . . . . . . . . . . . . . . . 19-12
Table 19-5.
Non-Architectural Performance Events of the Processor Core Supported by Broadwell Microarchitecture . . . . . . 19-13
Table 19-6.
Intel® TSX Performance Event Addendum in Processors Based on Broadwell Microarchitecture . . . . . . . . . . . . . . . . 19-21
Table 19-7.
Non-Architectural Performance Events in the Processor Core of
4th Generation Intel® Core™ Processors19-21
Table 19-8.
Intel TSX Performance Events in Processors Based on Haswell Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
Table 19-9.
Non-Architectural Uncore Performance Events in the 4th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . 19-32
Table 19-10.
Non-Architectural Performance Events Applicable only to the Processor Core of
Intel® Xeon® Processor E5 v3 Family19-33
Table 19-11.
Non-Architectural Performance Events In the Processor Core of
3rd Generation Intel® Core™ i7, i5, i3 Processors19-34
Table 19-12.
Non-Architectural Performance Events Applicable Only to the Processor Core of
Intel® Xeon® Processor E5 v2 Family and Intel® Xeon® Processor E7 v2 Family19-42
Table 19-13.
Non-Architectural Performance Events In the Processor Core Common to 2nd Generation Intel® Core™ i7-2xxx, Intel®
Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series and Intel® Xeon® Processors E3 and E5 Family19-43
Table 19-14.
Non-Architectural Performance Events applicable only to the Processor core for 2nd Generation Intel® Core™ i7-2xxx,
Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series19-52
Table 19-15.
Non-Architectural Performance Events Applicable only to the Processor Core of
Intel® Xeon® Processor E5 Family19-54
Table 19-16.
Non-Architectural Performance Events In the Processor Uncore for 2nd Generation
Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series19-56
Table 19-17.
Non-Architectural Performance Events In the Processor Core for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series19-57
Table 19-18.
Non-Architectural Performance Events In the Processor Uncore for
Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series19-74
Table 19-19.
Non-Architectural Performance Events In the Processor Core for
Processors Based on Intel® Microarchitecture Code Name Westmere19-86
Table 19-20.
Non-Architectural Performance Events In the Processor Uncore for
Processors Based on Intel® Microarchitecture Code Name Westmere19-102
Table 19-21.
Non-Architectural Performance Events for Processors Based on Enhanced Intel Core Microarchitecture. . . . . . .19-117
Table 19-22.
Fixed-Function Performance Counter and Pre-defined Performance Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-117
Table 19-23.
Non-Architectural Performance Events in Processors Based on Intel® Core™ Microarchitecture. . . . . . . . . . . . . . . .19-118
Table 19-24.
Non-Architectural Performance Events for the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-143
Table 19-25.
Performance Events for Silvermont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-149
Table 19-26.
Non-Architectural Performance Events for 45 nm, 32 nm Intel® Atom™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . .19-154
Table 19-27.
Non-Architectural Performance Events in Intel® Core™ Solo and Intel® Core™ Duo Processors. . . . . . . . . . . . . . . . . .19-168
Table 19-28.
Performance Monitoring Events Supported by Intel NetBurst® Microarchitecture
for Non-Retirement Counting19-173
Table 19-29.
Performance Monitoring Events For Intel NetBurst® Microarchitecture
for At-Retirement Counting19-191
Table 19-30.
Intel NetBurst® Microarchitecture Model-Specific Performance Monitoring Events
(For Model Encoding 3, 4 or 6)19-195
Table 19-32.
List of Metrics Available for Execution Tagging (For Execution Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-196
Table 19-33.
List of Metrics Available for Replay Tagging (For Replay Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-196
Table 19-31.
List of Metrics Available for Front_end Tagging (For Front_end Event Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-196
Table 19-34.
Event Mask Qualification for Logical Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-198
Table 19-35.
Performance Monitoring Events on Intel
®
Pentium
®
M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-203
Table 19-36.
Performance Monitoring Events Modified on Intel
®
Pentium
®
M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-204
Table 19-37.
Events That Can Be Counted with the P6 Family Performance-Monitoring Counters. . . . . . . . . . . . . . . . . . . . . . . . . .19-205
Table 19-38.
Events That Can Be Counted with Pentium Processor Performance-Monitoring Counters. . . . . . . . . . . . . . . . . . . . .19-214
Table 20-1.
Real-Address Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Table 20-2.
Software Interrupt Handling Methods While in Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17
Table 21-1.
Characteristics of 16-Bit and 32-Bit Program Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
Table 22-1.
New Instruction in the Pentium Processor and Later IA-32 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
Table 22-3.
EM and MP Flag Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16
Table 22-2.
Recommended Values of the EM, MP, and NE Flags for Intel486 SX Microprocessor/Intel 487 SX Math Coprocessor
System22-16
Table 22-4.
Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment . . . . . . . . . . . 22-21