19-12 Vol. 3B

PERFORMANCE-MONITORING EVENTS

Table 19-8 lists performance events supporting Intel TSX (see Section 18.11.5) and the events are applicable to 
processors based on Skylake microarchitecture. Where Skylake microarchitecture implements TSX-related event 
semantics that differ from Table 19-8, they are listed in Table 19-4.

D1H

01H

MEM_LOAD_RETIRED.L1_HIT

Retired load instructions with L1 cache hits as data 

sources.

PSDLA

D1H

02H

MEM_LOAD_RETIRED.L2_HIT

Retired load instructions with L2 cache hits as data 

sources.

PSDLA

D1H

04H

MEM_LOAD_RETIRED.L3_HIT

Retired load instructions with L3 cache hits as data 

sources.

PSDLA

D1H

08H

MEM_LOAD_RETIRED.L1_MISS

Retired load instructions missed L1 cache as data 

sources.

PSDLA

D1H

10H

MEM_LOAD_RETIRED.L2_MISS

Retired load instructions missed L2. Unknown data 

source excluded.

PSDLA

D1H

20H

MEM_LOAD_RETIRED.L3_MISS

Retired load instructions missed L3. Excludes unknown 

data source.

PSDLA

D1H

40H

MEM_LOAD_RETIRED.FB_HIT

Retired load instructions where data sources were load 

uops missed L1 but hit FB due to preceding miss to the 

same cache line with data not ready.

PSDLA

D2H

01H

MEM_LOAD_L3_HIT_RETIRED.X

SNP_MISS

Retired load instructions where data sources were L3 

hit and cross-core snoop missed in on-pkg core cache.

PSDLA

D2H

02H

MEM_LOAD_L3_HIT_RETIRED.X

SNP_HIT

Retired load Instructions where data sources were L3 

and cross-core snoop hits in on-pkg core cache.

PSDLA

D2H

04H

MEM_LOAD_L3_HIT_RETIRED.X

SNP_HITM

Retired load instructions where data sources were HitM 

responses from shared L3.

PSDLA

D2H

08H

MEM_LOAD_L3_HIT_RETIRED.X

SNP_NONE

Retired load instructions where data sources were hits 

in L3 without snoops required.

PSDLA

E6H

01H

BACLEARS.ANY

Number of front end re-steers due to BPU 

misprediction.

F0H

40H

L2_TRANS.L2_WB

L2 writebacks that access L2 cache.

F1H

07H

L2_LINES_IN.ALL

L2 cache lines filling L2.

CMSK1: Counter Mask = 1 required; CMSK4: CounterMask = 4 required; CMSK6: CounterMask = 6 required; CMSK8: CounterMask = 8 

required; CMSK10: CounterMask = 10 required; CMSK12: CounterMask = 12 required; CMSK16: CounterMask = 16 required; CMSK20: 

CounterMask = 20 required.
AnyT: AnyThread = 1 required.
INV: Invert = 1 required.
EDG: EDGE = 1 required.
PSDLA: Also supports PEBS and DataLA.
PS: Also supports PEBS.

Table 19-4.  Intel® TSX Performance Event Addendum in Processors based on Skylake Microarchitecture

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment

54H

02H

TX_MEM.ABORT_CAPACITY

Number of times a transactional abort was signaled due 

to a data capacity limitation for transactional reads or 

writes.

Table 19-3.  Non-Architectural Performance Events of the Processor Core Supported by Skylake Microarchitecture

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment