Vol. 3B 19-195

PERFORMANCE-MONITORING EVENTS

machine_clear 

This event increments according to the mask bit specified while the 

entire pipeline of the machine is cleared. Specify one of the mask bit 

to select the cause.

ESCR restrictions

MSR_CRU_ESCR2
MSR_CRU_ESCR3

Counter numbers 

per ESCR

ESCR2: 12, 13, 16
ESCR3: 14, 15, 17

ESCR Event Select

02H

ESCR[31:25]

ESCR Event Mask

Bit 
0: CLEAR

ESCR[24:9]

Counts for a portion of the many cycles while the machine is cleared 

for any cause. Use Edge triggering for this bit only to get a count of 

occurrence versus a duration.

2:  MOCLEAR

6: SMCLEAR

Increments each time the machine is cleared due to memory ordering 

issues.
Increments each time the machine is cleared due to self-modifying 

code issues.

CCCR Select

05H

CCCR[15:13]

Can Support PEBS

No

Table 19-30.  Intel NetBurst® Microarchitecture Model-Specific Performance Monitoring Events 

(For Model Encoding 3, 4 or 6)

Event Name

Event Parameters

 Parameter Value

Description

instr_completed 

This event counts instructions that have completed and retired 

during a clock cycle. Mask bits specify whether the instruction is 

bogus or non-bogus and whether they are:

ESCR restrictions

MSR_CRU_ESCR0
MSR_CRU_ESCR1

Counter numbers 

per ESCR

ESCR0: 12, 13, 16
ESCR1: 14, 15, 17

ESCR Event Select

07H

ESCR[31:25]

ESCR Event Mask

Bit 
0: NBOGUS
1: BOGUS

ESCR[24:9]

Non-bogus instructions
Bogus instructions

CCCR Select

04H

CCCR[15:13]

Event Specific 

Notes

This metric differs from instr_retired, since it counts instructions 

completed, rather than the number of times that instructions started.

Can Support PEBS

No

Table 19-29.  Performance Monitoring Events For Intel NetBurst® Microarchitecture 

for At-Retirement Counting (Contd.)

Event Name

Event Parameters

 Parameter Value

Description