Vol. 3A
li
CONTENTS
PAGE
Table 38-26.
Layout of Version Array Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16
Table 38-27.
Content of an Enclave Page Cache Map Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-17
Table 39-1.
Illegal Instructions Inside an Enclave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-13
Table 40-1.
GPR, x87 Synthetic States on Asynchronous Enclave Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3
Table 41-1.
Register Usage of Privileged Enclave Instruction Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1
Table 41-2.
Register Usage of Unprivileged Enclave Instruction Leaf Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2
Table 41-3.
Error or Information Codes for Intel® SGX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2
Table 41-4.
List of Internal CREG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3
Table 41-5.
Concurrency Restrictions of EADD with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-11
Table 41-6.
Concurrency Restrictions of EADD with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-12
Table 41-7.
Concurrency Restrictions of EAUG with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-15
Table 41-8.
Concurrency Restrictions of EAUG with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-16
Table 41-9.
EBLOCK Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18
Table 41-10.
Concurrency Restrictions of EBLOCK with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18
Table 41-11.
Concurrency Restrictions of EBLOCK with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-19
Table 41-12.
Concurrency Restrictions of ECREATE with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-21
Table 41-13.
Concurrency Restrictions of ECREATE with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-21
Table 41-14.
EDBGRD Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-25
Table 41-15.
Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-26
Table 41-16.
Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-26
Table 41-17.
EDBGWR Return Value in RAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-28
Table 41-18.
Concurrency Restrictions of EDBGWR with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-29
Table 41-19.
Concurrency Restrictions of EDBGWR with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-29
Table 41-20.
Concurrency Restrictions of EEXTEND with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-31
Table 41-21.
Concurrency Restrictions of EEXTEND with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-32
Table 41-22.
EINIT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-35
Table 41-23.
Concurrency Restrictions of EINIT with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-36
Table 41-24.
Concurrency Restrictions of EINIT with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-36
Table 41-25.
ELDB/ELDU Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-41
Table 41-26.
Concurrency Restrictions of ELDB/ELDU with Intel® SGX Instructions - 1of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-41
Table 41-27.
Concurrency Restrictions of ELDB/ELDU with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-42
Table 41-28.
EMODPR Return Value in RAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-46
Table 41-29.
Concurrency Restrictions of EMODPR with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-46
Table 41-30.
Concurrency Restrictions of EMODPR with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-47
Table 41-31.
EMODT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-49
Table 41-32.
Concurrency Restrictions of EMODT with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-49
Table 41-33.
Concurrency Restrictions of EMODT with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-50
Table 41-34.
Concurrency Restrictions of EPA with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-52
Table 41-35.
Concurrency Restrictions of EPA with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-52
Table 41-36.
EREMOVE Return Value in RAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-54
Table 41-37.
Concurrency Restrictions of EREMOVE with Other Intel® SGX Operations 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-55
Table 41-38.
Concurrency Restrictions of EREMOVE with Other Intel® SGX Operations 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-55
Table 41-39.
ETRACK Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-57
Table 41-40.
Concurrency Restrictions of ETRACK with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-57
Table 41-41.
Concurrency Restrictions of ETRACK with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-57
Table 41-42.
ETRACK Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-58
Table 41-43.
EWB Return Value in RAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-59
Table 41-44.
Concurrency Restrictions of EWB with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-59
Table 41-45.
Concurrency Restrictions of EWB with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-59
Table 41-46.
EACCEPT Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-65
Table 41-47.
Concurrency Restrictions of EACCEPT with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-65
Table 41-48.
Concurrency Restrictions of EACCEPT with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-66
Table 41-49.
EACCEPTCOPY Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-69
Table 41-50.
Concurrency Restrictions of EACCEPTCOPY with Intel® SGX Instructions - 1of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-70
Table 41-51.
Concurrency Restrictions of EACCEPTCOPY with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-70
Table 41-52.
Concurrency Restrictions of EENTER with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-74
Table 41-53.
Concurrency Restrictions of EENTER with Intel® SGX Instructions - 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-74
Table 41-54.
Concurrency Restrictions of EEXIT with Intel® SGX Instructions - 1of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-81
Table 41-55.
Concurrency Restrictions of EEXIT with Intel® SGX Instructions - 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-81
Table 41-56.
Key Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-85
Table 41-57.
EGETKEY Return Value in RAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-85
Table 41-58.
Concurrency Restrictions of EGETKEY with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-85
Table 41-59.
Concurrency Restrictions of EGETKEY with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-86
Table 41-60.
Concurrency Restrictions of EMODPE with Other Intel® SGX Operations 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-92
Table 41-61.
Concurrency Restrictions of EMODPE with Other Intel® SGX Operations 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-92