41-26 Vol. 3D
SGX INSTRUCTION REFERENCES
Concurrency Restrictions
Operation
Temp Variables in EDBGRD Operational Flow
TMP_MODE64 ((IA32_EFER.LMA = 1) && (CS.L = 1));
IF ( (TMP_MODE64 = 1) and (DS:RCX is not 8Byte Aligned) )
THEN #GP(0); FI;
IF ( (TMP_MODE64 = 0) and (DS:RCX is not 4Byte Aligned) )
THEN #GP(0); FI;
IF (DS:RCX does not resolve within an EPC)
THEN #PF(DS:RCX); FI;
(* make sure no other Intel SGX instruction is accessing EPCM *)
IF (Other EPCM modifying instructions executing)
THEN #GP(0); FI;
IF (EPCM(DS:RCX). VALID = 0)
THEN #PF(DS:RCX); FI;
(* make sure that DS:RCX (SOURCE) is pointing to a PT_REG or PT_TCS or PT_VA *)
IF ( (EPCM(DS:RCX).PT ≠ PT_REG) and (EPCM(DS:RCX).PT ≠ PT_TCS) and (EPCM(DS:RCX).PT ≠ PT_VA))
THEN #PF(DS:RCX); FI;
(* If source is a TCS, then make sure that the offset into the page is not beyond the TCS size*)
IF ( ( EPCM(DS:RCX). PT = PT_TCS) and ((DS:RCX) & FFFH
≥
SGX_TCS_LIMIT) )
THEN #GP(0); FI;
Table 41-15. Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 1 of 2
Operation
EEXIT
EADD
EBLOCK
ECRE
ATE
EDBGRD/
WR
EENTER/
ERESUME
EEXTEND
EGETKEY
EINIT
ELDB/ELDU
EPA
Param TCS SSA SECS Targ SECS Targ SECS SECS
Targ SECS TCS SSA SECS Targ SECS Param SECS SECS Targ VA
SECS VA
EDBGRD
Targ
Y
Y
N
Y
N
Y
Y
Y
Y
Y
N
N
Y
N
SECS
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Table 41-16. Concurrency Restrictions of EDBGRD with Other Intel® SGX Operations 2 of 2
Operation
EREMOVE
EREPORT
ETRACK
EWB
EAUG
EMODPE
EMODPR
EMODT
EACCEPT
EACCEPTCOPY
Param Targ SECS Param SECS SECS
SRC VA SECS Targ SECS Targ SECI
NFO
Targ SEC
S
Targ SEC
S
Targ SECI
NFO
SECS Targ SR
C
SECI
NFO
EDBGRD
Targ
N
Y
N
N
Y
N
Y
Y
Y
N
Y
Y
Y
SECS
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Name
Type
Size (Bits)
Description
TMP_MODE64
Binary
1
((IA32_EFER.LMA = 1) && (CS.L = 1))
TMP_SECS
64
Physical address of SECS of the enclave to which source operand belongs