Vol. 3A 10-13

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

mode. Not supported for the LVT CMCI register, the LVT thermal monitor 
register, or the LVT performance counter register.

Delivery Status (Read Only)

Indicates the interrupt delivery status, as follows:

0 (Idle)

There is currently no activity for this interrupt source, or the previous in-
terrupt from this source was delivered to the processor core and accepted.

1 (Send Pending)

Indicates that an interrupt from this source has been delivered to the pro-
cessor core but has not yet been accepted (see Section 10.5.5, “Local In-
terrupt Acceptance”).

Figure 10-8.  Local Vector Table (LVT)

31

0

7

Vector

Timer Mode

00: One-shot

01: Periodic

12

15

16

17

18

Delivery Mode
000: Fixed

100: NMI

Mask

†

0: Not Masked
1: Masked

Address: FEE0 0350H

Value After Reset: 0001 0000H

Reserved

12

13

15

16

Vector

31

0

7

8

10

Address: FEE0 0360H
Address: FEE0 0370H

Vector

Vector

Error

LINT1

LINT0

Value after Reset: 0001 0000H

Address: FEE0 0320H

111: ExtlNT

All other combinations
are reserved

Interrupt Input

Pin Polarity

Trigger Mode
0: Edge

1: Level

Remote

IRR

Delivery Status

0: Idle
1: Send Pending

Timer

13

11

8

11

14

17

Address: FEE0 0340H

Performance

Vector

Thermal

Vector

Mon. Counters

Sensor

Address: FEE0 0330H

† (Pentium 4 and Intel Xeon processors.) When a 

performance monitoring counters interrupt is generated, 
the mask bit for its associated LVT entry is set.

010: SMI

101: INIT

19

10: TSC-Deadline

Vector

CMCI

Address: FEE0 02F0H