Vol. 3B 18-5
PERFORMANCE MONITORING
A processor that supports architectural performance monitoring may not support all the predefined architectural
performance events (Table 18-1). The non-zero bits in CPUID.0AH:EBX indicate the events that are not available.
The behavior of each architectural performance event is expected to be consistent on all processors that support
that event. Minor variations between microarchitectures are noted below:
•
UnHalted Core Cycles — Event select 3CH, Umask 00H
This event counts core clock cycles when the clock signal on a specific core is running (not halted). The counter
does not advance in the following conditions:
— an ACPI C-state other than C0 for normal operation
— HLT
— STPCLK# pin asserted
— being throttled by TM1
— during the frequency switching phase of a performance state transition (see Chapter 14, “Power and
The performance counter for this event counts across performance state transitions using different core clock
frequencies
•
Instructions Retired — Event select C0H, Umask 00H
This event counts the number of instructions at retirement. For instructions that consist of multiple micro-ops,
this event counts the retirement of the last micro-op of the instruction. An instruction with a REP prefix counts
as one instruction (not per iteration). Faults before the retirement of the last micro-op of a multi-ops instruction
are not counted.
This event does not increment under VM-exit conditions. Counters continue counting during hardware
interrupts, traps, and inside interrupt handlers.
•
UnHalted Reference Cycles — Event select 3CH, Umask 01H
This event counts reference clock cycles while the clock signal on the core is running. The reference clock
operates at a fixed frequency, irrespective of core frequency changes due to performance state transitions.
Processors may implement this behavior differently. See Table 19-23 and Table 19-27 in Chapter 19, “Perfor-
mance-Monitoring Events.”
•
Last Level Cache References — Event select 2EH, Umask 4FH
This event counts requests originating from the core that reference a cache line in the last level cache. The
event count includes speculation and cache line fills due to the first-level cache hardware prefetcher, but may
exclude cache line fills due to other hardware-prefetchers.
Because cache hierarchy, cache sizes and other implementation-specific characteristics; value comparison to
estimate performance differences is not recommended.
•
Last Level Cache Misses — Event select 2EH, Umask 41H
This event counts each cache miss condition for references to the last level cache. The event count may include
speculation and cache line fills due to the first-level cache hardware prefetcher, but may exclude cache line fills
due to other hardware-prefetchers.
Because cache hierarchy, cache sizes and other implementation-specific characteristics; value comparison to
estimate performance differences is not recommended.
•
Branch Instructions Retired — Event select C4H, Umask 00H
This event counts branch instructions at retirement. It counts the retirement of the last micro-op of a branch
instruction.
•
All Branch Mispredict Retired — Event select C5H, Umask 00H
5
Branch Instruction Retired
00H
C4H
6
Branch Misses Retired
00H
C5H
Table 18-1. UMask and Event Select Encodings for Pre-Defined Architectural Performance Events