Vol. 3A 10-15

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

•

Bit 2: Send Accept Error.
Set when the local APIC detects that a message it sent was not accepted by any APIC on the APIC bus. Used 
only on P6 family and Pentium processors.

•

Bit 3: Receive Accept Error.
Set when the local APIC detects that the message it received was not accepted by any APIC on the APIC bus, 
including itself. Used only on P6 family and Pentium processors.

•

Bit 4: Redirectable IPI.
Set when the local APIC detects an attempt to send an IPI with the lowest-priority delivery mode and the local 
APIC does not support the sending of such IPIs. This bit is used on some Intel Core and Intel Xeon processors. 
As noted in Section 10.6.2, the ability of a processor to send a lowest-priority IPI is model-specific and should 
be avoided.

•

Bit 5: Send Illegal Vector.
Set when the local APIC detects an illegal vector (one in the range 0 to 15) in the message that it is sending. 
This occurs as the result of a write to the ICR (in both xAPIC and x2APIC modes) or to SELF IPI register (x2APIC 
mode only) with an illegal vector.
If the local APIC does not support the sending of lowest-priority IPIs and software writes the ICR to send a 
lowest-priority IPI with an illegal vector, the local APIC sets only the “redirectible IPI” error bit. The interrupt is 
not processed and hence the “Send Illegal Vector” bit is not set in the ESR.

•

Bit 6: Receive Illegal Vector.
Set when the local APIC detects an illegal vector (one in the range 0 to 15) in an interrupt message it receives 
or in an interrupt generated locally from the local vector table or via a self IPI. Such interrupts are not be 
delivered to the processor; the local APIC will never set an IRR bit in the range 0 to 15.

•

Bit 7: Illegal Register Address
Set when the local APIC is in xAPIC mode and software attempts to access a register that is reserved in the 
processor's local-APIC register-address space; see Table 10-1. (The local-APIC register-address space 
comprises the 4 KBytes at the physical address specified in the IA32_APIC_BASE MSR.) Used only on Intel 
Core, Intel Atom™, Pentium 4, Intel Xeon, and P6 family processors.
In x2APIC mode, software accesses the APIC registers using the RDMSR and WRMSR instructions. Use of one 
of these instructions to access a reserved register cause a general-protection exception (see Section 
10.12.1.3). They do not set the “Illegal Register Access” bit in the ESR.

Figure 10-9.  Error Status Register (ESR)

Address: FEE0 0280H
Value after reset: 0H

31

0

Reserved

7

8

1

2

3

4

5

6

Illegal Register Address

1

Received Illegal Vector
Send Illegal Vector
Redirectable IPI

2

Receive Accept Error

3

Send Accept Error

3

Receive Checksum Error

3

Send Checksum Error

3

2. Used only by some Intel Core and Intel Xeon processors;

reserved on other processors.

1. Used only by Intel Core, Pentium 4, Intel Xeon, and P6 family

processors; reserved on the Pentium processor.

NOTES:

3. Used only by the P6 family and Pentium processors;

reserved on Intel Core, Pentium 4 and Intel Xeon processors.