Vol. 3C 35-311

MODEL-SPECIFIC REGISTERS (MSRS)

402H

1026

IA32_MC0_ADDR

Unique

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the IA32_MC0_STATUS 

register is clear. When not implemented in the processor, all reads 

and writes to this MSR will cause a general-protection exception.

404H

1028

IA32_MC1_CTL

Unique

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

405H

1029

IA32_MC1_STATUS

Unique

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

406H

1030

IA32_MC1_ADDR

Unique

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the IA32_MC1_STATUS 

register is clear. When not implemented in the processor, all reads 

and writes to this MSR will cause a general-protection exception.

408H

1032

IA32_MC2_CTL

Unique

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

409H

1033

IA32_MC2_STATUS

Unique

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

40AH

1034

IA32_MC2_ADDR

Unique

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 
The IA32_MC2_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the IA32_MC2_STATUS 

register is clear. When not implemented in the processor, all reads 

and writes to this MSR will cause a general-protection exception.

40CH

1036

MSR_MC4_CTL

Unique

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

40DH

1037

MSR_MC4_STATUS

Unique

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

40EH

1038

MSR_MC4_ADDR

Unique

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the MSR_MC4_STATUS 

register is clear. When not implemented in the processor, all reads 

and writes to this MSR will cause a general-protection exception.

410H

1040

IA32_MC3_CTL

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

411H

1041

IA32_MC3_STATUS

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

412H

1042

MSR_MC3_ADDR

Unique

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the MSR_MC3_STATUS 

register is clear. When not implemented in the processor, all reads 

and writes to this MSR will cause a general-protection exception.

413H

1043

MSR_MC3_MISC

Unique

414H

1044

MSR_MC5_CTL

Unique

415H

1045

MSR_MC5_STATUS

Unique

416H

1046

MSR_MC5_ADDR

Unique

417H

1047

MSR_MC5_MISC

Unique

480H

1152

IA32_VMX_BASIC

Unique

Reporting Register of Basic VMX Capabilities (R/O)
See Table 35-2.
See Appendix A.1, “Basic VMX Information”
(If CPUID.01H:ECX.[bit 9])

Table 35-44.  MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV 

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec