4-32 Vol. 3A

PAGING

As noted in Section 4.3, Section 4.4.2, and Section 4.5, there is no translation for a linear address if the translation 
process for that address would use a paging-structure entry in which the P flag (bit 0) is 0 or one that sets a 
reserved bit. If there is a translation for a linear address, its access rights are determined as specified in Section 
4.6.
When Intel® Software Guard Extensions (Intel® SGX) are enabled, the processor may deliver exception 14 for 
reasons unrelated to paging. See Section 38.3, “Access-control Requirements” and Section 38.19, “Enclave Page 
Cache Map (EPCM)” in Chapter 38, “Enclave Access Control and Data Structures.” Such an exception is called an 
SGX-induced page fault. The processor uses the error code to distinguish SGX-induced page faults from ordinary 
page faults.
Figure 4-12 illustrates the error code that the processor provides on delivery of a page-fault exception. The 
following items explain how the bits in the error code describe the nature of the page-fault exception:

•

P flag (bit 0).
This flag is 0 if there is no translation for the linear address because the P flag was 0 in one of the paging-
structure entries used to translate that address.

•

W/R (bit 1).
If the access causing the page-fault exception was a write, this flag is 1; otherwise, it is 0. This flag describes 
the access causing the page-fault exception, not the access rights specified by paging.

•

U/S (bit 2).
If a user-mode access caused the page-fault exception, this flag is 1; it is 0 if a supervisor-mode access did so. 
This flag describes the access causing the page-fault exception, not the access rights specified by paging. User-
mode and supervisor-mode accesses are defined in Section 4.6.

•

RSVD flag (bit 3).
This flag is 1 if there is no translation for the linear address because a reserved bit was set in one of the paging-
structure entries used to translate that address. (Because reserved bits are not checked in a paging-structure 
entry whose P flag is 0, bit 3 of the error code can be set only if bit 0 is also set.

1

)

Figure 4-12.  Page-Fault Error Code

The fault was caused by a non-present page.
The fault was caused by a page-level protection violation.

The access causing the fault was a read.
The access causing the fault was a write.

A supervisor-mode access caused the fault.
A user-mode access caused the fault.

31

0

Reserved

1

2

3

4

The fault was not caused by reserved bit violation.
The fault was caused by a reserved bit set to 1 in some

P

0

1

W/R

0

1

U/S

0

RSVD

0
1

1

I/D

I/D

0  The fault was not caused by an instruction fetch.
1 The fault was caused by an instruction fetch.

P

W/R

U/S

RSVD

paging-structure entry.

PK 5

PK

0  The fault was not caused by protection keys.
1 There was a protection-key violation.

SGX

The fault is not related to SGX.

0
1 The fault resulted from violation of SGX-specific access-control

requirements.

Reserved

SG
X

15