Vol. 3C 35-65

MODEL-SPECIFIC REGISTERS (MSRS)

30BH

779

IA32_FIXED_CTR2

Unique

Fixed-Function Performance Counter Register 2 (R/W) 
See Table 35-2.

345H

837

IA32_PERF_CAPABILITIES

Shared

See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”

38DH

909

IA32_FIXED_CTR_CTRL

Unique

Fixed-Function-Counter Control Register (R/W) 
See Table 35-2.

38EH

910

IA32_PERF_GLOBAL_

STATUS

Unique

See Table 35-2. See Section 18.4.2, “Global Counter Control 

Facilities.” 

38FH

911

IA32_PERF_GLOBAL_CTRL

Unique

See Table 35-2. See Section 18.4.2, “Global Counter Control 

Facilities.”

390H

912

IA32_PERF_GLOBAL_OVF_

CTRL

Unique

See Table 35-2. See Section 18.4.2, “Global Counter Control 

Facilities.”

3F1H

1009

MSR_PEBS_ENABLE

Unique

See Table 35-2. See Section 18.4.4, “Precise Event Based Sampling 

(PEBS).”

0

Enable PEBS on IA32_PMC0. (R/W)

400H

1024

IA32_MC0_CTL

Shared

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

401H

1025

IA32_MC0_STATUS

Shared

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

402H

1026

IA32_MC0_ADDR

Shared

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the IA32_MC0_STATUS 

register is clear. 
When not implemented in the processor, all reads and writes to this 

MSR will cause a general-protection exception.

404H

1028

IA32_MC1_CTL

Shared

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

405H

1029

IA32_MC1_STATUS

Shared

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

408H

1032

IA32_MC2_CTL

Shared

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

409H

1033

IA32_MC2_STATUS

Shared

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

40AH

1034

IA32_MC2_ADDR

Shared

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 
The IA32_MC2_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the IA32_MC2_STATUS 

register is clear. 
When not implemented in the processor, all reads and writes to this 

MSR will cause a general-protection exception.

40CH

1036

IA32_MC3_CTL

Shared

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

40DH

1037

IA32_MC3_STATUS

Shared

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

40EH

1038

IA32_MC3_ADDR

Shared

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the MSR_MC3_STATUS 

register is clear. 
When not implemented in the processor, all reads and writes to this 

MSR will cause a general-protection exception.

410H

1040

IA32_MC4_CTL

Shared

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

411H

1041

IA32_MC4_STATUS

Shared

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

Table 35-4.  MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family (Contd.)

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec