Vol. 3C 35-53

MODEL-SPECIFIC REGISTERS (MSRS)

30AH

778

IA32_FIXED_CTR1

Unique

Fixed-Function Performance Counter Register 1 (R/W) 
See Table 35-2.

30AH

778

MSR_PERF_FIXED_CTR1

Unique

Fixed-Function Performance Counter Register 1 (R/W) 

30BH

779

IA32_FIXED_CTR2

Unique

Fixed-Function Performance Counter Register 2 (R/W) 
See Table 35-2.

30BH

779

MSR_PERF_FIXED_CTR2

Unique

Fixed-Function Performance Counter Register 2 (R/W) 

345H

837

IA32_PERF_CAPABILITIES

Unique

See Table 35-2. See Section 17.4.1, “IA32_DEBUGCTL MSR.”

345H

837

MSR_PERF_CAPABILITIES

Unique

RO. This applies to processors that do not support architectural 

perfmon version 2.

5:0

LBR Format. See Table 35-2.

6

PEBS  Record  Format. 

7

PEBSSaveArchRegs. See Table 35-2.

63:8

Reserved.

38DH

909

IA32_FIXED_CTR_CTRL

Unique

Fixed-Function-Counter Control Register (R/W) 
See Table 35-2.

38DH

909

MSR_PERF_FIXED_CTR_

CTRL

Unique

Fixed-Function-Counter Control Register (R/W) 

38EH

910

IA32_PERF_GLOBAL_

STATUS

Unique

See Table 35-2. See Section 18.4.2, “Global Counter Control 

Facilities.” 

38EH

910

MSR_PERF_GLOBAL_STATU

S

Unique

See Section 18.4.2, “Global Counter Control Facilities.”

38FH

911

IA32_PERF_GLOBAL_CTRL

Unique

See Table 35-2. See Section 18.4.2, “Global Counter Control 

Facilities.”

38FH

911

MSR_PERF_GLOBAL_CTRL

Unique

See Section 18.4.2, “Global Counter Control Facilities.”

390H

912

IA32_PERF_GLOBAL_OVF_

CTRL

Unique

See Table 35-2. See Section 18.4.2, “Global Counter Control 

Facilities.”

390H

912

MSR_PERF_GLOBAL_OVF_

CTRL

Unique

See Section 18.4.2, “Global Counter Control Facilities.”

3F1H

1009

MSR_PEBS_ENABLE

Unique

See Table 35-2. See Section 18.4.4, “Precise Event Based Sampling 

(PEBS).”

0

Enable PEBS on IA32_PMC0. (R/W)

400H

1024

IA32_MC0_CTL

Unique

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

401H

1025

IA32_MC0_STATUS

Unique

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

402H

1026

IA32_MC0_ADDR

Unique

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or 

contains no address if the ADDRV flag in the IA32_MC0_STATUS 

register is clear. 
When not implemented in the processor, all reads and writes to this 

MSR will cause a general-protection exception.

Table 35-3.  MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec