Vol. 3C 27-9
VM EXITS
— For VM exits caused as part of EOI virtualization (Section 29.1.4), bits 7:0 of the exit qualification are set
to vector of the virtual interrupt that was dismissed by the EOI virtualization. Bits above bit 7 are cleared.
— For APIC-write VM exits (Section 29.4.3.3), bits 11:0 of the exit qualification are set to the page offset of
the write access that caused the VM exit.
1
Bits above bit 11 are cleared.
— For a VM exit due to a page-modification log-full event (Section 28.2.5), only bit 12 of the exit qualification
is defined, and only in some cases. It is undefined in the following cases:
•
If the “NMI exiting” VM-execution control is 1 and the “virtual NMIs” VM-execution control is 0.
•
If the VM exit sets the valid bit in the IDT-vectoring information field (see Section 27.2.3).
Otherwise, it is defined as follows:
•
If the “virtual NMIs” VM-execution control is 0, the page-modification log-full event was caused by a
memory access as part of execution of the IRET instruction, and blocking by NMI (see Table 24-3) was
in effect before execution of IRET, bit 12 is set to 1.
•
If the “virtual NMIs” VM-execution control is 1,the page-modification log-full event was caused by a
memory access as part of execution of the IRET instruction, and virtual-NMI blocking was in effect
before execution of IRET, bit 12 is set to 1.
•
For all other relevant VM exits, bit 12 is cleared to 0.
For these VM exits, all bits other than bit 12 are undefined.
•
Guest-linear address. For some VM exits, this field receives a linear address that pertains to the VM exit. The
field is set for different VM exits as follows:
— VM exits due to attempts to execute LMSW with a memory operand. In these cases, this field receives the
linear address of that operand. Bits 63:32 are cleared if the logical processor was not in 64-bit mode before
the VM exit.
— VM exits due to attempts to execute INS or OUTS for which the relevant segment is usable (if the relevant
segment is not usable, the value is undefined). (ES is always the relevant segment for INS; for OUTS, the
relevant segment is DS unless overridden by an instruction prefix.) The linear address is the base address
of relevant segment plus (E)DI (for INS) or (E)SI (for OUTS). Bits 63:32 are cleared if the logical processor
was not in 64-bit mode before the VM exit.
1. Execution of WRMSR with ECX = 83FH (self-IPI MSR) can lead to an APIC-write VM exit; the exit qualification for such an APIC-write
VM exit is 3F0H.
Table 27-7. Exit Qualification for EPT Violations
Bit Position(s)
Contents
0
Set if the access causing the EPT violation was a data read.
1
1
Set if the access causing the EPT violation was a data write.
2
Set if the access causing the EPT violation was an instruction fetch.
3
The logical-AND of bit 0 in the EPT paging-structure entries used to translate the guest-physical address of the
access causing the EPT violation (indicates that the guest-physical address was readable).
2
4
The logical-AND of bit 1 in the EPT paging-structure entries used to translate the guest-physical address of the
access causing the EPT violation (indicates that the guest-physical address was writeable).
5
The logical-AND of bit 2 in the EPT paging-structure entries used to translate the guest-physical address of the
access causing the EPT violation (indicates that the guest-physical address was executable).
6
Reserved (cleared to 0).
7
Set if the guest linear-address field is valid.
The guest linear-address field is valid for all EPT violations except those resulting from an attempt to load the
guest PDPTEs as part of the execution of the MOV CR instruction.