13-16 Vol. 1

MANAGING STATE USING THE XSAVE FEATURE SET

If XSTATE_BV[1] = 0, the compacted form XRSTOR initializes MXCSR to 1F80H. (This differs from the standard 
from of XRSTOR, which loads MXCSR from the XSAVE area whenever either RFBM[1] or RFBM[2] is set.)
State component i is set to its initial configuration as indicated above if RFBM[i] = 1 and XSTATE_BV[i] =  0  — 
even if XCOMP_BV[i] =  0. This is true for all values of i, including 0 (x87 state) and 1 (SSE state).

•

If XSTATE_BV[i] = 1, the state component is loaded with data from the XSAVE area.

1

 See Section 13.5 for 

specifics for each state component and for details regarding mode-specific operation and operation determined 
by instruction prefixes. See Section 13.13 for details regarding faults caused by memory accesses.
State components 0 and 1 are located in the legacy region of the XSAVE area (see Section 13.4.1). Each state 
component i, 2 ≤ i ≤ 62, is located in the extended region; the compacted form of the XRSTOR instruction uses 

the compacted format for the extended region (see Section 13.4.3).

The MXCSR register is part of SSE state (see Section 13.5.2) and is thus loaded from memory if RFBM[1] = 
XSTATE_BV[i] = 1. The compacted form of XRSTOR does not consider RFBM[2] (AVX) when determining whether 
to update MXCSR. (This is a difference from the standard form of XRSTOR.) The compacted form of XRSTOR causes 
a general-protection exception (#GP) if it would load MXCSR with an illegal value.

13.8.3 

XRSTOR and the Init and Modified Optimizations

Execution of the XRSTOR instruction causes the processor to update is tracking for the init and modified optimiza-
tions (see Section 13.6). The following items provide details:

•

The processor updates its tracking for the init optimization as follows:
— If  RFBM[i] =  0,  XINUSE[i] is not changed.
— If  RFBM[i] =  1  and  XSTATE_BV[i] = 0, state component i may be tracked as init; XINUSE[i] may be set to 

0 or 1. (As noted in Section 13.6, a processor need not implement the init optimization for state component 
i; a processor that does not do so implicitly maintains XINUSE[i] = 1 at all times.)

— If  RFBM[i] =  1  and  XSTATE_BV[i] = 1, state component i is tracked as not init; XINUSE[i] is set to 1.

•

The processor updates its tracking for the modified optimization and records information about the XRSTOR 
execution for future interaction with the XSAVEOPT and XSAVES instructions (see Section 13.9 and Section 
13.11) as follows:
— If  RFBM[i] = 0, state component i is tracked as modified; XMODIFIED[i] is set to 1.
— If  RFBM[i] = 1, state component i may be tracked as unmodified; XMODIFIED[i] may be set to 0 or 1. (As 

noted in Section 13.6, a processor need not implement the modified optimization for state component i; a 
processor that does not do so implicitly maintains XMODIFIED[i] = 1 at all times.)

— XRSTOR_INFO is set to the 4-tuple 



w,x,y,z



, where w is the CPL (0); x is 1 if the logical processor is in VMX 

non-root operation and 0 otherwise; y is the linear address of the XSAVE area; and z is XCOMP_BV. In 
particular, the standard form of XRSTOR always sets z to all zeroes, while the compacted form of XRSTORS 
never does so (because it sets at least bit 63 to 1).

13.9 

OPERATION OF XSAVEOPT

The operation of XSAVEOPT is similar to that of XSAVE. Unlike XSAVE, XSAVEOPT uses the init optimization (by 
which it may omit saving state components that are in their initial configuration) and the modified optimization (by 
which it may omit saving state components that have not been modified since the last execution of XRSTOR); see 
Section 13.6. See Section 13.2 for details of how to determine whether XSAVEOPT is supported.
The XSAVEOPT instruction takes a single memory operand, which is an XSAVE area. In addition, the register pair 
EDX:EAX is an implicit operand used as a state-component bitmap (see Section 13.1) called the instruction 
mask. The logical (bitwise) AND of XCR0 and the instruction mask is the requested-feature bitmap (RFBM) of 
the user state components to be saved.

1. Earlier fault checking ensured that, if the instruction has reached this point in execution and XSTATE_BV[i] is 1, then XCOMP_BV[i] is 

also 1.