13-6 Vol. 1

MANAGING STATE USING THE XSAVE FEATURE SET

state and software can execute MPX instructions. If XCR0[7:5] is 111b, the XSAVE feature set can be used to 
manage AVX-512 state and software can execute AVX-512 instructions. If XCR0[9] = 1, the XSAVE feature set 
can be used to manage PKRU state.

The IA32_XSS MSR (with MSR index DA0H) is zero coming out of RESET. If CR4.OSXSAVE = 1, 
CPUID.(EAX=0DH,ECX=1):EAX[3] = 1, and CPL = 0, executing the WRMSR instruction with ECX = DA0H writes 
the 64-bit value in EDX:EAX to the IA32_XSS MSR (EAX is written to IA32_XSS[31:0] and EDX to 
IA32_XSS[63:32]). The following items provide details regarding individual bits in the IA32_XSS MSR:

•

IA32_XSS[8] is associated with PT state (see Section 13.5.6). Software can use XSAVES and XRSTORS to 
manage PT state only if IA32_XSS[8] = 1. The value of IA32_XSS[8] does not determine whether software can 
use Intel Processor Trace (the feature can be used even if IA32_XSS[8] = 0).

•

IA32_XSS[63:9] and IA32_XSS[7:0] are reserved.

1

 Executing the WRMSR instruction causes a general-

protection fault (#GP) if ECX = DA0H and any corresponding bit in EDX:EAX is not 0. These bits in XCR0 are all 
0 coming out of RESET.

The IA32_XSS MSR is 0 coming out of RESET.
There is no mechanism by which software operating with CPL > 0 can discover the value of the IA32_XSS MSR.

13.4 XSAVE 

AREA

The XSAVE feature set includes instructions that save and restore the XSAVE-managed state components to and 
from memory: XSAVE, XSAVEOPT, XSAVEC, and XSAVES (for saving); and XRSTOR and XRSTORS (for restoring). 
The processor organizes the state components in a region of memory called an XSAVE area. Each of the save and 
restore instructions takes a memory operand that specifies the 64-byte aligned base address of the XSAVE area on 
which it operates.
Every XSAVE area has the following format:

•

The legacy region. The legacy region of an XSAVE area comprises the 512 bytes starting at the area’s base 
address. It is used to manage the state components for x87 state and SSE state. The legacy region is described 
in more detail in Section 13.4.1.

•

The XSAVE header. The XSAVE header of an XSAVE area comprises the 64 bytes starting at an offset of 512 
bytes from the area’s base address. The XSAVE header is described in more detail in Section 13.4.2.

•

The extended region. The extended region of an XSAVE area starts at an offset of 576 bytes from the area’s 
base address. It is used to manage the state components other than those for x87 state and SSE state. The 
extended region is described in more detail in Section 13.4.3. The size of the extended region is determined by 
which state components the processor supports and which bits have been set in XCR0 and IA32_XSS (see 
Section 13.3).

13.4.1 

Legacy Region of an XSAVE Area

The legacy region of an XSAVE area comprises the 512 bytes starting at the area’s base address. It has the same 
format as the FXSAVE area (see Section 10.5.1). The XSAVE feature set uses the legacy area for x87 state (state 
component 0) and SSE state (state component 1). Table 13-1 illustrates the format of the first 416 bytes of the 
legacy region of an XSAVE area.

1. Bit 9 and bits 7:0 correspond to user state components. Since bits can be set in the IA32_XSS MSR only for supervisor state compo-

nents, those bits of the MSR must be 0.

Table 13-1.  Format of the Legacy Region of an XSAVE Area

15 14

13  12

11 10

9

8

7

6

5 

4

3

2

1

0

FIP[63:48] or 

reserved

 FCS or 

FIP[47:32]

 FIP[31:0]

FOP

Rsvd. FTW

FSW

FCW

0

MXCSR_MASK

MXCSR

FDP[63:48] 

or reserved

 FDS or 

FDP[47:32]

 FDP[31:0]

16