13-2 Vol. 1
MANAGING STATE USING THE XSAVE FEATURE SET
— State component 6 is used for the upper 256 bits of the registers ZMM0–ZMM15. These 16 256-bit values
are denoted ZMM0_H–ZMM15_H (ZMM_Hi256 state).
— State component 7 is used for the 16 512-bit registers ZMM16–ZMM31 (Hi16_ZMM state).
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Bit 8 corresponds to the state component used for the Intel Processor Trace MSRs (PT state).
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Bit 9 corresponds to the state component used for the protection-key feature’s register PKRU (PKRU state).
See Section 13.5.7.
Bits in the range 62:10 are not currently defined in state-component bitmaps and are reserved for future expan-
sion. As individual state component is defined within bits 62:10, additional sub-sections are updated within Section
13.5 over time. Bit 63 is used for special functionality in some bitmaps and does not correspond to any state
component.
The state component corresponding to bit i of state-component bitmaps is called state component i. Thus, x87
state is state component 0; SSE state is state component 1; AVX state is state component 2; MPX state comprises
state components 3–4; AVX-512 state comprises state components 5–7; PT state is state component 8; and PKRU
state is state component 9.
The XSAVE feature set uses state-component bitmaps in multiple ways. Most of the instructions use an implicit
operand (in EDX:EAX), called the instruction mask, which is the state-component bitmap that specifies the state
components on which the instruction operates.
Some state components are user state components, and they can be managed by the entire XSAVE feature set.
Other state components are supervisor state components, and they can be managed only by XSAVES and
XRSTORS. All the state components corresponding to bits in the range 9:0 are user state components, except PT
state (corresponding to bit 8), which is a supervisor state component.
Extended control register XCR0 contains a state-component bitmap that specifies the user state components that
software has enabled the XSAVE feature set to manage. If the bit corresponding to a state component is clear in
XCR0, instructions in the XSAVE feature set will not operate on that state component, regardless of the value of the
instruction mask.
The IA32_XSS MSR (index DA0H) contains a state-component bitmap that specifies the supervisor state compo-
nents that software has enabled XSAVES and XRSTORS to manage (XSAVE, XSAVEC, XSAVEOPT, and XRSTOR
cannot manage supervisor state components). If the bit corresponding to a state component is clear in the
IA32_XSS MSR, XSAVES and XRSTORS will not operate on that state component, regardless of the value of the
instruction mask.
Some XSAVE-supported features can be used only if XCR0 has been configured so that the features’ state compo-
nents can be managed by the XSAVE feature set. (This applies only to features with user state components.) Such
state components and features are XSAVE-enabled. In general, the processor will not modify (or allow modifica-
tion of) the registers of a state component of an XSAVE-enabled feature if the bit corresponding to that state
component is clear in XCR0. (If software clears such a bit in XCR0, the processor preserves the corresponding state
component.) If an XSAVE-enabled feature has not been fully enabled in XCR0, execution of any instruction defined
for that feature causes an invalid-opcode exception (#UD).
As will be explained in Section 13.3, the XSAVE feature set is enabled only if CR4.OSXSAVE[bit 18] = 1. If
CR4.OSXSAVE = 0, the processor treats XSAVE-enabled state features and their state components as if all bits in
XCR0 were clear; the state components cannot be modified and the features’ instructions cannot be executed.
The state components for x87 state, for SSE state, for PT state, and for PKRU state are XSAVE-managed but the
corresponding features are not XSAVE-enabled. Processors allow modification of this state, as well as execution of
x87 FPU instructions and SSE instructions and use of Intel Processor Trace and protection keys, regardless of the
value of CR4.OSXSAVE and XCR0.
13.2
ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVE-
SUPPORTED FEATURES
A processor enumerates support for the XSAVE feature set and for features supported by that feature set using the
CPUID instruction. The following items provide specific details:
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CPUID.1:ECX.XSAVE[bit 26] enumerates general support for the XSAVE feature set: