Vol. 1 11-3

PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)

information on the functions of these flags see Section 10.2.3.4, “Denormals-Are-Zeros,” and Section 10.2.3.3, 
“Flush-To-Zero.”

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MMX registers — These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed 
integer data. They are also used to hold operands for some operations performed between MMX and XMM 
registers. MMX registers are referenced by the names MM0 through MM7.

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General-purpose registers — The eight general-purpose registers (see Figure 3-5) are used along with the 
existing IA-32 addressing modes to address operands in memory. MMX and XMM registers cannot be used to 
address memory. The general-purpose registers are also used to hold operands for some SSE2 instructions. 
These registers are referenced by the names EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.

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EFLAGS register — This 32-bit register (see Figure 3-8) is used to record the results of some compare 
operations.

11.2.1 

SSE2 in 64-Bit Mode and Compatibility Mode

In compatibility mode, SSE2 extensions function like they do in protected mode. In 64-bit mode, eight additional 
XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. 
Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5.
Some SSE2 instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access 64-
bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored.

11.2.2 

Compatibility of SSE2 Extensions with SSE, MMX

Technology and x87 FPU Programming Environment

SSE2 extensions do not introduce any new state to the IA-32 execution environment beyond that of SSE. SSE2 
extensions represent an enhancement of SSE extensions; they are fully compatible and share the same state infor-
mation. SSE and SSE2 instructions can be executed together in the same instruction stream without the need to 
save state when switching between instruction sets.
XMM registers are independent of the x87 FPU and MMX registers; so SSE and SSE2 operations performed on XMM 
registers can be performed in parallel with x87 FPU or MMX technology operations (see Section 11.6.7, “Interaction 
of SSE/SSE2 Instructions with x87 FPU and MMX Instructions”).
The FXSAVE and FXRSTOR instructions save and restore the SSE and SSE2 states along with the x87 FPU and MMX 
states.

11.2.3 Denormals-Are-Zeros 

Flag

The denormals-are-zeros flag (bit 6 in the MXCSR register) was introduced into the IA-32 architecture with the 
SSE2 extensions. See Section 10.2.3.4, “Denormals-Are-Zeros,” for a description of this flag.

11.3 SSE2 

DATA 

TYPES

SSE2 extensions introduced one 128-bit packed floating-point data type and four 128-bit SIMD integer data types 
to the IA-32 architecture (see Figure 11-2). 

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Packed double-precision floating-point — This 128-bit data type consists of two IEEE 64-bit double-
precision floating-point values packed into a double quadword. (See Figure 4-3 for the layout of a 64-bit 
double-precision floating-point value; refer to Section 4.2.2, “Floating-Point Data Types,” for a detailed 
description of double-precision floating-point values.)

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128-bit packed integers — The four 128-bit packed integer data types can contain 16 byte integers, 8 word 
integers, 4 doubleword integers, or 2 quadword integers. (Refer to Section 4.6.2, “128-Bit Packed SIMD Data 
Types,” for a detailed description of the 128-bit packed integers.)