11-4 Vol. 1
PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS 2 (INTEL® SSE2)
All of these data types are operated on in XMM registers or memory. Instructions are provided to convert between
these 128-bit data types and the 64-bit and 32-bit data types.
The address of a 128-bit packed memory operand must be aligned on a 16-byte boundary, except in the following
cases:
•
a MOVUPD instruction which supports unaligned accesses
•
scalar instructions that use an 8-byte memory operand that is not subject to alignment requirements
Figure 4-2 shows the byte order of 128-bit (double quadword) and 64-bit (quadword) data types in memory.
11.4 SSE2
INSTRUCTIONS
The SSE2 instructions are divided into four functional groups:
•
Packed and scalar double-precision floating-point instructions
•
64-bit and 128-bit SIMD integer instructions
•
128-bit extensions of SIMD integer instructions introduced with the MMX technology and the SSE extensions
•
Cacheability-control and instruction-ordering instructions
The following sections provide more information about each group.
11.4.1
Packed and Scalar Double-Precision Floating-Point Instructions
The packed and scalar double-precision floating-point instructions are divided into the following sub-groups:
•
Data movement instructions
•
Arithmetic instructions
•
Comparison instructions
•
Conversion instructions
•
Logical instructions
•
Shuffle instructions
The packed double-precision floating-point instructions perform SIMD operations similarly to the packed single-
precision floating-point instructions (see Figure 11-3). Each source operand contains two double-precision
Figure 11-2. Data Types Introduced with the SSE2 Extensions
128-Bit Packed Word Integers
128-Bit Packed Byte Integers
128-Bit Packed Doubleword
Integers
0
127
0
127
0
127
0
127
0
127
128-Bit Packed Quadword
Integers
128-Bit Packed Double-
Precision Floating-Point
64 63