19-20 Vol. 3B

PERFORMANCE-MONITORING EVENTS

Table 19-8 lists performance events supporting Intel TSX (see Section 18.11.5) and the events are applicable to 
processors based on Broadwell microarchitecture. Where Broadwell microarchitecture implements TSX-related 
event semantics that differ from Table 19-8, they are listed in Table 19-6.

D1H

08H

MEM_LOAD_UOPS_RETIRED.L1_

MISS

Retired load uops missed L1 cache as data sources.

Supports PEBS and 

DataLA.

D1H

10H

MEM_LOAD_UOPS_RETIRED.L2_

MISS

Retired load uops missed L2. Unknown data source 

excluded.

Supports PEBS and 

DataLA.

D1H

20H

MEM_LOAD_UOPS_RETIRED.L3_

MISS

Retired load uops missed L3. Excludes unknown data 

source.

Supports PEBS and 

DataLA.

D1H

40H

MEM_LOAD_UOPS_RETIRED.HIT

_LFB

Retired load uops where data sources were load 

uops missed L1 but hit FB due to preceding miss to 

the same cache line with data not ready.

Supports PEBS and 

DataLA.

D2H

01H

MEM_LOAD_UOPS_L3_HIT_RETI

RED.XSNP_MISS

Retired load uops where data sources were L3 hit 

and cross-core snoop missed in on-pkg core cache.

Supports PEBS and 

DataLA.

D2H

02H

MEM_LOAD_UOPS_L3_HIT_RETI

RED.XSNP_HIT

Retired load uops where data sources were L3 and 

cross-core snoop hits in on-pkg core cache.

Supports PEBS and 

DataLA.

D2H

04H

MEM_LOAD_UOPS_L3_HIT_RETI

RED.XSNP_HITM

Retired load uops where data sources were HitM 

responses from shared L3.

Supports PEBS and 

DataLA.

D2H

08H

MEM_LOAD_UOPS_L3_HIT_RETI

RED.XSNP_NONE

Retired load uops where data sources were hits in 

L3 without snoops required.

Supports PEBS and 

DataLA.

D3H

01H

MEM_LOAD_UOPS_L3_MISS_RE

TIRED.LOCAL_DRAM

Retired load uops where data sources missed L3 but 

serviced from local dram. 

Supports PEBS and 

DataLA.

F0H

01H

L2_TRANS.DEMAND_DATA_RD

Demand data read requests that access L2 cache.

F0H

02H

L2_TRANS.RFO

RFO requests that access L2 cache.

F0H

04H

L2_TRANS.CODE_RD

L2 cache accesses when fetching instructions.

F0H

08H

L2_TRANS.ALL_PF

Any MLC or L3 HW prefetch accessing L2, including 

rejects. 

F0H

10H

L2_TRANS.L1D_WB

L1D writebacks that access L2 cache.

F0H

20H

L2_TRANS.L2_FILL

L2 fill requests that access L2 cache.

F0H

40H

L2_TRANS.L2_WB

L2 writebacks that access L2 cache.

F0H

80H

L2_TRANS.ALL_REQUESTS

Transactions accessing L2 pipe.

F1H

01H

L2_LINES_IN.I

L2 cache lines in I state filling L2.

Counting does not cover 

rejects.

F1H

02H

L2_LINES_IN.S

L2 cache lines in S state filling L2.

Counting does not cover 

rejects.

F1H

04H

L2_LINES_IN.E

L2 cache lines in E state filling L2.

Counting does not cover 

rejects.

F1H

07H

L2_LINES_IN.ALL

L2 cache lines filling L2.

Counting does not cover 

rejects.

F2H

05H

L2_LINES_OUT.DEMAND_CLEAN Clean L2 cache lines evicted by demand.

Table 19-5.  Non-Architectural Performance Events of the Processor Core Supported by Broadwell 

Microarchitecture (Contd.)

Event

Num.

Umask

Value

Event Mask Mnemonic

Description

Comment