18-40 Vol. 3B

PERFORMANCE MONITORING

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Data Source: The encoded value indicates the origin of the data obtained by the load instruction. The encoding 
is shown in Table 18-24. In the descriptions local memory refers to system memory physically attached to a 
processor package, and remote memory referrals to system memory physically attached to another processor 
package. 

The layout of MSR_PEBS_LD_LAT_THRESHOLD is shown in Figure 18-23.

Bits 15:0 specifies the threshold load latency in core clock cycles. Performance events with latencies greater than 
this value are counted in IA32_PMCx and their latency information is reported in the PEBS record. Otherwise, they 
are ignored. The minimum value that may be programmed in this field is 3.

Table 18-24.  Data Source Encoding for Load Latency Record

Encoding Description
00H

Unknown L3 cache miss

01H

Minimal latency core cache hit. This request was satisfied by the L1 data cache.

02H

Pending core cache HIT. Outstanding core cache miss to same cache-line address was already underway.

03H

This data request was satisfied by the L2.

04H

L3 HIT. Local or Remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping).

05H

L3 HIT. Local or Remote home requests that hit the L3 cache and was serviced by another processor core with a cross 

core snoop where no modified copies were found. (clean).

06H

L3 HIT. Local or Remote home requests that hit the L3 cache and was serviced by another processor core with a cross 

core snoop where modified copies were found. (HITM).

07H

1

NOTES:

1. Bit 7 is supported only for processor with CPUID DisplayFamily_DisplayModel signature of 06_2A, and 06_2E; otherwise it is 

reserved.

Reserved/LLC Snoop HitM. Local or Remote home requests that hit the last level cache and was serviced by another 

core with a cross core snoop where modified copies found

08H

L3 MISS. Local homed requests that missed the L3 cache and was serviced by forwarded data following a cross 

package snoop where no modified copies found. (Remote home requests are not counted).

09H

Reserved

0AH

L3 MISS. Local home requests that missed the L3 cache and was serviced by local DRAM (go to shared state).

0BH

L3 MISS. Remote home requests that missed the L3 cache and was serviced by remote DRAM (go to shared state).

0CH

L3 MISS. Local home requests that missed the L3 cache and was serviced by local DRAM (go to exclusive state).

0DH

L3 MISS. Remote home requests that missed the L3 cache and was serviced by remote DRAM (go to exclusive state).

0EH

I/O, Request of input/output operation

0FH

The request was to un-cacheable memory.

Figure 18-23.  Layout of MSR_PEBS_LD_LAT MSR 

1615

0

Reserved

63

THRHLD - Load latency threshold

RESET Value — 00000000_00000000H