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Vol. 3C 35-297

MODEL-SPECIFIC REGISTERS (MSRS)

406H

1030 IA32_MC1_ADDR

0, 1, 2, 3, 

4, 6

Shared

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.” 
The IA32_MC1_ADDR register is either not 

implemented or contains no address if the ADDRV 

flag in the IA32_MC1_STATUS register is clear. 
When not implemented in the processor, all reads 

and writes to this MSR will cause a general-

protection exception.

407H

1031 IA32_MC1_MISC

Shared

See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC1_MISC MSR is either not 

implemented or does not contain additional 

information if the MISCV flag in the 

IA32_MC1_STATUS register is clear. 
When not implemented in the processor, all reads 

and writes to this MSR will cause a general-

protection exception.

408H

1032 IA32_MC2_CTL

0, 1, 2, 3, 

4, 6

Shared

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

409H

1033 IA32_MC2_STATUS

0, 1, 2, 3, 

4, 6

Shared

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

40AH

1034 IA32_MC2_ADDR

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not 

implemented or contains no address if the ADDRV 

flag in the IA32_MC2_STATUS register is clear. 

When not implemented in the processor, all reads 

and writes to this MSR will cause a general-

protection exception.

40BH

1035 IA32_MC2_MISC

See Section 15.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC2_MISC MSR is either not 

implemented or does not contain additional 

information if the MISCV flag in the 

IA32_MC2_STATUS register is clear. 
When not implemented in the processor, all reads 

and writes to this MSR will cause a general-

protection exception.

40CH

1036 IA32_MC3_CTL

0, 1, 2, 3, 

4, 6

Shared

See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”

40DH

1037 IA32_MC3_STATUS

0, 1, 2, 3, 

4, 6

Shared

See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”

40EH

1038 IA32_MC3_ADDR

0, 1, 2, 3, 

4, 6

Shared

See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC3_ADDR register is either not 

implemented or contains no address if the ADDRV 

flag in the IA32_MC3_STATUS register is clear. 
When not implemented in the processor, all reads 

and writes to this MSR will cause a general-

protection exception.

Table 35-41.  MSRs in the Pentium® 4 and Intel® Xeon® Processors  (Contd.)

Register 

Address

Register Name

Fields and Flags

Model 

Avail-

ability

Shared/

Unique

1

Bit Description

 Hex

Dec