Vol. 3C 35-73
MODEL-SPECIFIC REGISTERS (MSRS)
63:0
CORE C6 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C6
states. Counts at the TSC Frequency.
400H
1024
IA32_MC0_CTL
Module
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Module
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Module
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC0_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
404H
1028
IA32_MC1_CTL
Module
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Module
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
408H
1032
IA32_MC2_CTL
Module
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Module
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Module
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MC2_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
40CH
1036
IA32_MC3_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
IA32_MC3_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC3_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
410H
1040
IA32_MC4_CTL
Core
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC4_STATUS
Core
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
IA32_MC4_ADDR
Core
See Section 15.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the MSR_MC4_STATUS
register is clear.
When not implemented in the processor, all reads and writes to this
MSR will cause a general-protection exception.
414H
1044
IA32_MC5_CTL
Package
See Section 15.3.2.1, “IA32_MCi_CTL MSRs.”
415H
1045
IA32_MC5_STATUS
Package
See Section 15.3.2.2, “IA32_MCi_STATUS MSRS.”
Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom
Processors
Address
Register Name
Scope
Bit Description
Hex
Dec