Vol. 3A 4-23
PAGING
•
Because a PTE is identified using bits 47:12 of the linear address, every PTE maps a 4-KByte page (see
Table 4-19). The final physical address is computed as follows:
— Bits 51:12 are from the PTE.
— Bits 11:0 are from the original linear address.
If CR4.PKE = 1, the linear address’s protection key is the value of bits 62:59 of the PTE.
If a paging-structure entry’s P flag (bit 0) is 0 or if the entry sets any reserved bit, the entry is used neither to refer-
ence another paging-structure entry nor to map a page. There is no translation for a linear address whose transla-
tion would use such a paging-structure entry; a reference to such a linear address causes a page-fault exception
(see Section 4.7).
The following bits are reserved with IA-32e paging:
•
If the P flag of a paging-structure entry is 1, bits 51:MAXPHYADDR are reserved.
•
If the P flag of a PML4E is 1, the PS flag is reserved.
•
If 1-GByte pages are not supported and the P flag of a PDPTE is 1, the PS flag is reserved.
1
•
If the P flag and the PS flag of a PDPTE are both 1, bits 29:13 are reserved.
•
If the P flag and the PS flag of a PDE are both 1, bits 20:13 are reserved.
•
If IA32_EFER.NXE = 0 and the P flag of a paging-structure entry is 1, the XD flag (bit 63) is reserved.
A reference using a linear address that is successfully translated to a physical address is performed only if allowed
by the access rights of the translation; see Section 4.6.
Figure 4-11 gives a summary of the formats of CR3 and the IA-32e paging-structure entries. For the paging struc-
ture entries, it identifies separately the format of entries that map pages, those that reference other paging struc-
tures, and those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted because
they determine how a paging-structure entry is used.
1. See Section 4.1.4 for how to determine whether 1-GByte pages are supported.
Table 4-14. Format of an IA-32e PML4 Entry (PML4E) that References a Page-Directory-Pointer Table
Bit
Position(s)
Contents
0 (P)
Present; must be 1 to reference a page-directory-pointer table
1 (R/W)
Read/write; if 0, writes may not be allowed to the 512-GByte region controlled by this entry (see Section 4.6)
2 (U/S)
User/supervisor; if 0, user-mode accesses are not allowed to the 512-GByte region controlled by this entry (see
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access the page-directory-pointer table
referenced by this entry (see Section 4.9.2)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access the page-directory-pointer table
referenced by this entry (see Section 4.9.2)
5 (A)
Accessed; indicates whether this entry has been used for linear-address translation (see Section 4.8)
6
Ignored
7 (PS)
Reserved (must be 0)
11:8
Ignored