Page 120

4-16 Vol. 3A

PAGING

Figure 4-6. Linear-Address Translation to a 2-MByte Page using PAE Paging

Table 4-9. Format of a PAE Page-Directory Entry that Maps a 2-MByte Page

Bit

Position(s)

Contents

0 (P)

Present; must be 1 to map a 2-MByte page

1 (R/W)

Read/write; if 0, writes may not be allowed to the 2-MByte page referenced by this entry (see Section 4.6)

2 (U/S)

User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte page referenced by this entry (see Section

3 (PWT)

Page-level write-through; indirectly determines the memory type used to access the 2-MByte page referenced by

this entry (see Section 4.9)

4 (PCD)

Page-level cache disable; indirectly determines the memory type used to access the 2-MByte page referenced by this

5 (A)

Accessed; indicates whether software has accessed the 2-MByte page referenced by this entry (see Section 4.8)

6 (D)

Dirty; indicates whether software has written to the 2-MByte page referenced by this entry (see Section 4.8)

7 (PS)

Page size; must be 1 (otherwise, this entry references a page table; see Table 4-10)

8 (G)

Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise

11:9

Ignored

12 (PAT)

If the PAT is supported, indirectly determines the memory type used to access the 2-MByte page referenced by this

entry (see Section 4.9.2); otherwise, reserved (must be 0)

NOTES:

1. See Section 4.1.4 for how to determine whether the PAT is supported.

20:13

Reserved (must be 0)

(M–1):21

Physical address of the 2-MByte page referenced by this entry

62:M

Reserved (must be 0)

63 (XD)

If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from the 2-MByte page controlled by

this entry; see Section 4.6); otherwise, reserved (must be 0)