29-14 Vol. 3C

APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS

4. The processor writes zero to the EOI register in the local APIC; this dismisses the interrupt with the posted-

interrupt notification vector from the local APIC.

5. The logical processor performs a logical-OR of PIR into VIRR and clears PIR. No other agent can read or write a 

PIR bit (or group of bits) between the time it is read (to determine what to OR into VIRR) and when it is cleared.

6. The logical processor sets RVI to be the maximum of the old value of RVI and the highest index of all bits that 

were set in PIR; if no bit was set in PIR, RVI is left unmodified.

7. The logical processor evaluates pending virtual interrupts as described in Section 29.2.1.
The logical processor performs the steps above in an uninterruptible manner. If step #7 leads to recognition of a 
virtual interrupt, the processor may deliver that interrupt immediately.
Steps #1 to #7 above occur when the interrupt controller delivers an unmasked external interrupt to the CPU core. 
The following items consider certain cases of interrupt delivery:

•

Interrupt delivery can occur between iterations of a REP-prefixed instruction (after at least one iteration has 
completed but before all iterations have completed). If this occurs, the following items characterize processor 
state after posted-interrupt processing completes and before guest execution resumes:
— RIP references the REP-prefixed instruction;
— RCX, RSI, and RDI are updated to reflect the iterations completed; and
— RFLAGS.RF  =  1.

•

Interrupt delivery can occur when the logical processor is in the active, HLT, or MWAIT states. If the logical 
processor had been in the active or MWAIT state before the arrival of the interrupt, it is in the active state 
following completion of step #7; if it had been in the HLT state, it returns to the HLT state after step #7 (if a 
pending virtual interrupt was recognized, the logical processor may immediately wake from the HLT state).

•

Interrupt delivery can occur while the logical processor is in enclave mode. If the logical processor had been in 
enclave mode before the arrival of the interrupt, an Asynchronous Enclave Exit (AEX) may occur before the 
steps #1 to #7 (see Chapter 40, “Enclave Exiting Events”). If no AEX occurs before step #1 and a VM exit 
occurs at step #2, an AEX occurs before the VM exit is delivered.